From: Easwar Hariharan <eahariha@linux.microsoft.com>
To: stable@vger.kernel.org
Cc: Easwar Hariharan <eahariha@linux.microsoft.com>,
Jarred White <jarredwhite@linux.microsoft.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Vanshidhar Konda <vanshikonda@os.amperecomputing.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Subject: [PATCH 5.15.y 1/3] Revert "Revert "ACPI: CPPC: Use access_width over bit_width for system memory accesses""
Date: Tue, 30 Apr 2024 18:09:46 +0000 [thread overview]
Message-ID: <20240430180948.1435834-1-eahariha@linux.microsoft.com> (raw)
In-Reply-To: <2024042905-puppy-heritage-e422@gregkh>
This reverts commit b54c4632946ae42f2b39ed38abd909bbf78cbcc2 which was a
revert of a backport of commit 2f4a4d63a193be6fd530d180bb13c3592052904c
upstream to 5.15.y.
The original commit[1] fixed a kernel panic on boot on the Microsoft
Azure Cobalt 100 platform, but as reported by Vanshidhar Konda [2],
caused a regression in AmpereOne systems. While testing [2], there was
an additional bug found in [1] which resulted in [3]
[1] commit 2f4a4d63a193 ("ACPI: CPPC: Use access_width over bit_width for system memory accesses")
[2] commit f489c948028b ("ACPI: CPPC: Fix access width used for PCC registers")
[3] commit 05d92ee782ee ("ACPI: CPPC: Fix bit_offset shift in MASK_VAL() macro").
Cc: Jarred White <jarredwhite@linux.microsoft.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Vanshidhar Konda <vanshikonda@os.amperecomputing.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
---
drivers/acpi/cppc_acpi.c | 27 ++++++++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 7cc9183c8dc8..408b1fda5702 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -161,6 +161,13 @@ show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
+/* Check for valid access_width, otherwise, fallback to using bit_width */
+#define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
+
+/* Shift and apply the mask for CPC reads/writes */
+#define MASK_VAL(reg, val) ((val) >> ((reg)->bit_offset & \
+ GENMASK(((reg)->bit_width), 0)))
+
static ssize_t show_feedback_ctrs(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
@@ -762,8 +769,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
if (gas_t->address) {
void __iomem *addr;
+ size_t access_width;
- addr = ioremap(gas_t->address, gas_t->bit_width/8);
+ access_width = GET_BIT_WIDTH(gas_t) / 8;
+ addr = ioremap(gas_t->address, access_width);
if (!addr)
goto out_free;
cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
@@ -936,6 +945,7 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
{
int ret_val = 0;
void __iomem *vaddr = NULL;
+ int size;
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
struct cpc_reg *reg = ®_res->cpc_entry.reg;
@@ -955,7 +965,9 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
return acpi_os_read_memory((acpi_physical_address)reg->address,
val, reg->bit_width);
- switch (reg->bit_width) {
+ size = GET_BIT_WIDTH(reg);
+
+ switch (size) {
case 8:
*val = readb_relaxed(vaddr);
break;
@@ -974,12 +986,16 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
ret_val = -EFAULT;
}
+ if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
+ *val = MASK_VAL(reg, *val);
+
return ret_val;
}
static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
{
int ret_val = 0;
+ int size;
void __iomem *vaddr = NULL;
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
struct cpc_reg *reg = ®_res->cpc_entry.reg;
@@ -994,7 +1010,12 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
return acpi_os_write_memory((acpi_physical_address)reg->address,
val, reg->bit_width);
- switch (reg->bit_width) {
+ size = GET_BIT_WIDTH(reg);
+
+ if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
+ val = MASK_VAL(reg, val);
+
+ switch (size) {
case 8:
writeb_relaxed(val, vaddr);
break;
base-commit: b925f60c6ee7ec871d2d48575d0fde3872129c20
--
2.34.1
next prev parent reply other threads:[~2024-04-30 18:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-29 11:53 FAILED: patch "[PATCH] ACPI: CPPC: Fix access width used for PCC registers" failed to apply to 5.15-stable tree gregkh
2024-04-30 16:05 ` Easwar Hariharan
2024-04-30 17:41 ` Greg KH
2024-04-30 18:05 ` Easwar Hariharan
2024-04-30 18:27 ` Greg KH
2024-04-30 18:09 ` Easwar Hariharan [this message]
2024-04-30 18:09 ` [PATCH 5.15.y 2/3] ACPI: CPPC: Fix bit_offset shift in MASK_VAL() macro Easwar Hariharan
2024-04-30 18:09 ` [PATCH 5.15.y 3/3] ACPI: CPPC: Fix access width used for PCC registers Easwar Hariharan
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