Re: MHI MMIO endian issue

[Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>]

+ Paul Davey

On Tue, Apr 30, 2024 at 11:30:57PM +0200, Martin Fäcknitz wrote:
> Hello,
> 
> the function mhi_init_mmio configures MMIO registers using the reg_info
> table:
> 
>   eg_info[] = {
>     {
> 	  CCABAP_HIGHER,
>       upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
> 	},
> 	...
> 
>   mhi_write_reg(mhi_cntrl, base, reg_info[i].offset,
>     reg_info[i].val);
> 
> However, the values are in host byte orders, not in device byte order. I
> have a PPC64 system which is big endian, but the device is little
> endian. Without wrapping each value in eg_info using cpu_to_le32 the
> device (sdx55) doesn't response:
> 
>   cpu_to_le32(upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr))
> 
> Hard to believe i am the first one which has this issue? Let me know if
> i should make a patch.
> 

You are not the first one to try MHI on a big endian machine. Paul did that a
while ago and fixed some issues w.r.t endianess [1]. But I'm wondering how Paul
didn't hit the issue that you are seeing.

Anyway, I think the fix is to modify mhi_{read/write}_reg to accept '__le32'
for the 'val' parameter and fix all the callers.

I can cook a patch if needed, but won't be able to do so for atleast 2-3 weeks.

- Mani

[1] https://lore.kernel.org/mhi/20220212182117.49438-3-manivannan.sadhasivam@linaro.org/

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