From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
Cc: <kobayashi.da-06@jp.fujitsu.com>, <linux-cxl@vger.kernel.org>,
<y-goto@fujitsu.com>, <linux-pci@vger.kernel.org>, <mj@ucw.cz>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>
Subject: Re: [PATCH v6 2/2] cxl/pci: Add sysfs attribute for CXL 1.1 device link status
Date: Wed, 1 May 2024 13:16:51 +0100 [thread overview]
Message-ID: <20240501131651.00004cb7@Huawei.com> (raw)
In-Reply-To: <20240424050102.26788-3-kobayashi.da-06@fujitsu.com>
On Wed, 24 Apr 2024 14:01:02 +0900
"Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com> wrote:
> Add sysfs attribute for CXL 1.1 device link status to the cxl pci device.
>
> In CXL1.1, the link status of the device is included in the RCRB mapped to
> the memory mapped register area. Critically, that arrangement makes the
> link status and control registers invisible to existing PCI user tooling.
>
> Export those registers via sysfs with the expectation that PCI user
> tooling will alternatively look for these sysfs files when attempting to
> access to these CXL 1.1 endpoints registers.
>
> Signed-off-by: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
Looks good to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
prev parent reply other threads:[~2024-05-01 12:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-24 5:01 [PATCH v6 0/2] cxl: Export cxl1.1 device link status to sysfs Kobayashi,Daisuke
2024-04-24 5:01 ` [PATCH v6 1/2] cxl/core/regs: Add rcd_regs initialization at __rcrb_to_component() Kobayashi,Daisuke
2024-05-01 12:14 ` Jonathan Cameron
2024-04-24 5:01 ` [PATCH v6 2/2] cxl/pci: Add sysfs attribute for CXL 1.1 device link status Kobayashi,Daisuke
2024-05-01 12:16 ` Jonathan Cameron [this message]
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