[v2 12/16] net/mlx5/hws: dw order optimization code enhancement

[Itamar Gozlan <igozlan@nvidia.com>]

Improving code readability by following code styles such as mlx5dr prefix
and extracting a support check to an external function call.
Also, reducing unneeded static memory allocation using a bounded size
macro.

Fixes: 88ff41793e7a ("net/mlx5/hws: reorder STE fields to improve hash")
Cc: stable@dpdk.org

Signed-off-by: Itamar Gozlan <igozlan@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 39 ++++++++++++++-------------
 1 file changed, 20 insertions(+), 19 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 81d0e0e6df..cffbb7b589 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -31,6 +31,8 @@
 
 #define MLX5DR_DEFINER_QUOTA_BLOCK 0
 #define MLX5DR_DEFINER_QUOTA_PASS  2
+#define MLX5DR_DEFINER_MAX_ROW_LOG 32
+#define MLX5DR_DEFINER_HL_OPT_MAX 2
 
 /* Setter function based on bit offset and mask, for 32bit DW*/
 #define _DR_SET_32(p, v, byte_off, bit_off, mask) \
@@ -104,21 +106,13 @@
 	__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 	__mlx5_mask(typ, fld))
 
-#define MAX_ROW_LOG 31
-
-enum header_layout {
-	MLX5DR_HL_IPV4_SRC = 64,
-	MLX5DR_HL_IPV4_DST = 65,
-	MAX_HL_PRIO,
-};
-
 /* Each row (i) indicates a different matcher size, and each column (j)
  * represents {DW5, DW4, DW3, DW2, DW1, DW0}.
- * For values 0,..,2^i, and j (DW) 0,..,5: optimal_dist_dw[i][j] is 1 if the
+ * For values 0,..,2^i, and j (DW) 0,..,5: mlx5dr_optimal_dist_dw[i][j] is 1 if the
  * number of different hash results on these values equals 2^i, meaning this
  * DW hash distribution is complete.
  */
-int optimal_dist_dw[MAX_ROW_LOG][DW_SELECTORS_MATCH] = {
+int mlx5dr_optimal_dist_dw[MLX5DR_DEFINER_MAX_ROW_LOG][DW_SELECTORS_MATCH] = {
 	{1, 1, 1, 1, 1, 1}, {0, 1, 1, 0, 1, 0}, {0, 1, 1, 0, 1, 0},
 	{1, 0, 1, 0, 1, 0}, {0, 0, 0, 1, 1, 0}, {0, 1, 1, 0, 1, 0},
 	{0, 0, 0, 0, 1, 0}, {0, 1, 1, 0, 1, 0}, {0, 0, 0, 0, 0, 0},
@@ -3471,16 +3465,16 @@ mlx5dr_definer_find_best_range_fit(struct mlx5dr_definer *definer,
 
 static void mlx5dr_definer_optimize_order(struct mlx5dr_definer *definer, int num_log)
 {
-	uint8_t hl_prio[MAX_HL_PRIO - 1] = {MLX5DR_HL_IPV4_SRC,
-					    MLX5DR_HL_IPV4_DST,
-					    MAX_HL_PRIO};
+	uint8_t hl_prio[MLX5DR_DEFINER_HL_OPT_MAX];
 	int dw = 0, i = 0, j;
 	int *dw_flag;
 	uint8_t tmp;
 
-	dw_flag = optimal_dist_dw[num_log];
+	dw_flag = mlx5dr_optimal_dist_dw[num_log];
+	hl_prio[0] = __mlx5_dw_off(definer_hl, ipv4_src_dest_outer.source_address);
+	hl_prio[1] = __mlx5_dw_off(definer_hl, ipv4_src_dest_outer.destination_address);
 
-	while (hl_prio[i] != MAX_HL_PRIO) {
+	while (i < MLX5DR_DEFINER_HL_OPT_MAX) {
 		j = 0;
 		/* Finding a candidate to improve its hash distribution */
 		while (j < DW_SELECTORS_MATCH && (hl_prio[i] != definer->dw_selector[j]))
@@ -3632,6 +3626,16 @@ int mlx5dr_definer_compare(struct mlx5dr_definer *definer_a,
 	return 0;
 }
 
+static int
+mlx5dr_definer_optimize_order_supported(struct mlx5dr_definer *match_definer,
+					struct mlx5dr_matcher *matcher)
+{
+	return !mlx5dr_definer_is_jumbo(match_definer) &&
+	       !mlx5dr_matcher_req_fw_wqe(matcher) &&
+	       !mlx5dr_matcher_is_resizable(matcher) &&
+	       !mlx5dr_matcher_is_insert_by_idx(matcher);
+}
+
 static int
 mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,
 			   struct mlx5dr_definer *match_definer,
@@ -3693,10 +3697,7 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,
 		goto free_fc;
 	}
 
-	if (!mlx5dr_definer_is_jumbo(match_definer) &&
-	    !mlx5dr_matcher_req_fw_wqe(matcher) &&
-	    !mlx5dr_matcher_is_resizable(matcher) &&
-	    !mlx5dr_matcher_is_insert_by_idx(matcher))
+	if (mlx5dr_definer_optimize_order_supported(match_definer, matcher))
 		mlx5dr_definer_optimize_order(match_definer, matcher->attr.rule.num_log);
 
 	/* Find the range definer layout for match templates fcrs */
-- 
2.39.3