From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0B46C25B10 for ; Fri, 10 May 2024 08:10:13 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4VbM4h2sLtz3cfn for ; Fri, 10 May 2024 18:10:12 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=segher@kernel.crashing.org; receiver=lists.ozlabs.org) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by lists.ozlabs.org (Postfix) with ESMTP id 4VbM495ybVz3c4v for ; Fri, 10 May 2024 18:09:45 +1000 (AEST) Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 44A87c2O030764; Fri, 10 May 2024 03:07:38 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 44A87bmJ030763; Fri, 10 May 2024 03:07:37 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Fri, 10 May 2024 03:07:37 -0500 From: Segher Boessenkool To: Michael Ellerman Subject: Re: [PATCH 3/3] powerpc: Check only single values are passed to CPU/MMU feature checks Message-ID: <20240510080737.GY19790@gate.crashing.org> References: <20240509121248.270878-1-mpe@ellerman.id.au> <20240509121248.270878-3-mpe@ellerman.id.au> <20240509163456.GX19790@gate.crashing.org> <87ikzmmage.fsf@mail.lhotse> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87ikzmmage.fsf@mail.lhotse> User-Agent: Mutt/1.4.2.3i X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, May 10, 2024 at 04:45:37PM +1000, Michael Ellerman wrote: > Segher Boessenkool writes: > > On Thu, May 09, 2024 at 10:12:48PM +1000, Michael Ellerman wrote: > >> cpu_has_feature()/mmu_has_feature() are only able to check a single > >> feature at a time, but there is no enforcement of that. > >> > >> In fact, as fixed in the previous commit, there was code that was > >> passing multiple values to cpu_has_feature(). > >> > >> So add a check that only a single feature is passed using popcount. > >> > >> Note that the test allows 0 or 1 bits to be set, because some code > >> relies on cpu_has_feature(0) being false, the check with > >> CPU_FTRS_POSSIBLE ensures that. See for example CPU_FTR_PPC_LE. > > > > This btw is exactly > > > > BUILD_BUG_ON(feature & (feature - 1)); > > > > but the popcount is more readable :-) > > Yeah for those of us who don't see bits cascading in our sleep I think > the popcount is easier to understand ;) Absolutely :-) This is just one of the most well-known bittricks, for seeing if x is a power of two you write x && x & (x-1) but here you do not need to test for x not being zero. Hardly ever get to use that simpler thing, so it jumped out at me here :-) [ For understanding the x & (x-1) thing, it is perhaps easiest if you first consider an x with more than one bit set: x-1 will have the same topmost set bit. ] Segher