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From: Qingfang Deng <dqfext@gmail.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Xiao Wang <xiao.w.wang@intel.com>,
	Qingfang Deng <qingfang.deng@siflower.com.cn>
Subject: [PATCH v2] riscv: lib: relax assembly constraints in hweight
Date: Mon, 27 May 2024 17:24:04 +0800	[thread overview]
Message-ID: <20240527092405.134967-1-dqfext@gmail.com> (raw)

From: Qingfang Deng <qingfang.deng@siflower.com.cn>

rd and rs don't have to be the same. In some cases where rs needs to be
saved for later usage, this will save us some mv instructions.

Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
---
v2: updated title as suggested by Xiao.

 arch/riscv/include/asm/arch_hweight.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm/arch_hweight.h
index 85b2c443823e..613769b9cdc9 100644
--- a/arch/riscv/include/asm/arch_hweight.h
+++ b/arch/riscv/include/asm/arch_hweight.h
@@ -26,9 +26,9 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w)
 
 	asm (".option push\n"
 	     ".option arch,+zbb\n"
-	     CPOPW "%0, %0\n"
+	     CPOPW "%0, %1\n"
 	     ".option pop\n"
-	     : "+r" (w) : :);
+	     : "=r" (w) : "r" (w) :);
 
 	return w;
 
@@ -57,9 +57,9 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
 
 	asm (".option push\n"
 	     ".option arch,+zbb\n"
-	     "cpop %0, %0\n"
+	     "cpop %0, %1\n"
 	     ".option pop\n"
-	     : "+r" (w) : :);
+	     : "=r" (w) : "r" (w) :);
 
 	return w;
 
-- 
2.34.1


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WARNING: multiple messages have this Message-ID (diff)
From: Qingfang Deng <dqfext@gmail.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Xiao Wang <xiao.w.wang@intel.com>,
	Qingfang Deng <qingfang.deng@siflower.com.cn>
Subject: [PATCH v2] riscv: lib: relax assembly constraints in hweight
Date: Mon, 27 May 2024 17:24:04 +0800	[thread overview]
Message-ID: <20240527092405.134967-1-dqfext@gmail.com> (raw)

From: Qingfang Deng <qingfang.deng@siflower.com.cn>

rd and rs don't have to be the same. In some cases where rs needs to be
saved for later usage, this will save us some mv instructions.

Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
---
v2: updated title as suggested by Xiao.

 arch/riscv/include/asm/arch_hweight.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm/arch_hweight.h
index 85b2c443823e..613769b9cdc9 100644
--- a/arch/riscv/include/asm/arch_hweight.h
+++ b/arch/riscv/include/asm/arch_hweight.h
@@ -26,9 +26,9 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w)
 
 	asm (".option push\n"
 	     ".option arch,+zbb\n"
-	     CPOPW "%0, %0\n"
+	     CPOPW "%0, %1\n"
 	     ".option pop\n"
-	     : "+r" (w) : :);
+	     : "=r" (w) : "r" (w) :);
 
 	return w;
 
@@ -57,9 +57,9 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
 
 	asm (".option push\n"
 	     ".option arch,+zbb\n"
-	     "cpop %0, %0\n"
+	     "cpop %0, %1\n"
 	     ".option pop\n"
-	     : "+r" (w) : :);
+	     : "=r" (w) : "r" (w) :);
 
 	return w;
 
-- 
2.34.1


             reply	other threads:[~2024-05-27  9:24 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-27  9:24 Qingfang Deng [this message]
2024-05-27  9:24 ` [PATCH v2] riscv: lib: relax assembly constraints in hweight Qingfang Deng
2024-05-27 10:23 ` Wang, Xiao W
2024-05-27 10:23   ` Wang, Xiao W
2024-07-16 14:40 ` patchwork-bot+linux-riscv
2024-07-16 14:40   ` patchwork-bot+linux-riscv

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