From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75627154449 for ; Mon, 10 Jun 2024 18:35:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718044554; cv=none; b=Y85o2HONnSOhvlC+NodNs7yfI4ibuUbt0YyVSP6gy60hrdHUam3DDtn0q38aDUSzox95nRJcya8BVcJd2T/X4wGhMyR8/1i9wDXn6qv/h4q8mmUnoJ8VpSaFVRtR+Xh94rQyZRzl4a05V9pbEF+G4cVW/d92dB2UNBxEEiLI19E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718044554; c=relaxed/simple; bh=QWAT3iQia8dY5B2qRCiwXB7JLqWgNfQIUidwZFZo5vg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gHJTiqyQ/b2QQlz3eb58nprBW/kTWW5yMPcWl4dmsR6qzh9s44zmpPeZfQ0AFo3Fg/NnRYfy7vdqSJyabCaygdYYz1nJHW2ZxIBBOgzGPIax+3kQ506WTwSxeq8XWMzPfXR62UiROUGf1uhGaauYGGzeOdcfPtY2JvgIv+y0cRY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PQji/bxL; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PQji/bxL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718044552; x=1749580552; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QWAT3iQia8dY5B2qRCiwXB7JLqWgNfQIUidwZFZo5vg=; b=PQji/bxLvIeJmWJN8eGKgPYGj0f0iZ3vwG9hrKWXD2sfRXRMLHlkvDmm rtzXds+3Z31hVoLari/ehjiTJd+n21xGc9sOWGTmb5B4RK6ClfFd/TKzf 85hB3gRmXGoNSzVukV/Z+xdFNvQIYCieIqdhs/8U93WobDRGJipjQs2Nv X9ArMgZ8HOiPevnL8ijqhyJnXN0vQ7aGeJ8hXzRQWSn8kXFrmkdZYzGEW i44V7gUQ82/jq2n0+kN41k7hdtd6xndo7iBSnAdo1mr0i1RwKhC0NPgfn u9YKv0yuWKIgwp+wCExbI1fpaujnolFS/MDK7uH+Dw5ZnfikTTMzFF+YG Q==; X-CSE-ConnectionGUID: nj4wUhm9Qhm3BBCCIRVc+g== X-CSE-MsgGUID: b3nJI9QpRrCf8U9KukvXMg== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12004894" X-IronPort-AV: E=Sophos;i="6.08,227,1712646000"; d="scan'208";a="12004894" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2024 11:35:39 -0700 X-CSE-ConnectionGUID: JC+rwXPOQB+LVVj+PMgj/Q== X-CSE-MsgGUID: PXD/OZwfRvutt+FVvFhSzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,227,1712646000"; d="scan'208";a="43576607" Received: from agluck-desk3.sc.intel.com ([172.25.222.70]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2024 11:35:39 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v20 18/18] x86/resctrl: Update documentation with Sub-NUMA cluster changes Date: Mon, 10 Jun 2024 11:35:28 -0700 Message-ID: <20240610183528.349198-19-tony.luck@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240610183528.349198-1-tony.luck@intel.com> References: <20240610183528.349198-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit With Sub-NUMA Cluster (SNC) mode enabled the scope of monitoring resources is per-NODE instead of per-L3 cache. Backwards compatibility is mainatined by providing files in the mon_L3_XX directories that sum event counts for all SNC nodes sharing an L3 cache. New files provide per-SNC node event counts. Users should be aware that SNC mode also affects the amount of L3 cache available for allocation within each SNC node. Signed-off-by: Tony Luck --- Documentation/arch/x86/resctrl.rst | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index 627e23869bca..6695b7bc698d 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -375,6 +375,10 @@ When monitoring is enabled all MON groups will also contain: all tasks in the group. In CTRL_MON groups these files provide the sum for all tasks in the CTRL_MON group and all tasks in MON groups. Please see example section for more details on usage. + On systems with Sub-NUMA Cluster (SNC) enabled there are extra + directories for each node (located within the "mon_L3_XX" directory + for the L3 cache they occupy). These are named "mon_sub_L3_YY" + where "YY" is the node number. "mon_hw_id": Available only with debug option. The identifier used by hardware @@ -484,6 +488,29 @@ if non-contiguous 1s value is supported. On a system with a 20-bit mask each bit represents 5% of the capacity of the cache. You could partition the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. +Notes on Sub-NUMA Cluster mode +============================== +When SNC mode is enabled, Linux may load balance tasks between Sub-NUMA +nodes much more readily than between regular NUMA nodes since the CPUs +on Sub-NUMA nodes share the same L3 cache and the system may report +the NUMA distance between Sub-NUMA nodes with a lower value than used +for regular NUMA nodes. + +The top-level monitoring files in each "mon_L3_XX" directory provide +the sum of data across all SNC nodes sharing an L3 cache instance. +Users who bind tasks to the CPUs of a specific Sub-NUMA node can read +the "llc_occupancy", "mbm_total_bytes", and "mbm_local_bytes" in the +"mon_sub_L3_YY" directories to get node local data. + +Memory bandwidth allocation is still performed at the L3 cache +level. I.e. throttling controls are applied to all SNC nodes. + +L3 cache allocation bitmaps also apply to all SNC nodes. But note that +the amount of L3 cache represented by each bit is divided by the number +of SNC nodes per L3 cache. E.g. with a 100MB cache on a system with 10-bit +allocation masks each bit normally represents 10MB. With SNC mode enabled +with two SNC nodes per L3 cache, each bit would only represent 5MB. + Memory bandwidth Allocation and monitoring ========================================== -- 2.45.0