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charset=us-ascii Content-Disposition: inline In-Reply-To: <20240621112915.3434402-3-daire.mcnamara@microchip.com> Hi, kernel test robot noticed the following build warnings: [auto build test WARNING on a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6] url: https://github.com/intel-lab-lkp/linux/commits/daire-mcnamara-microchip-com/PCI-microchip-Fix-outbound-address-translation-tables/20240625-161731 base: a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6 patch link: https://lore.kernel.org/r/20240621112915.3434402-3-daire.mcnamara%40microchip.com patch subject: [PATCH v4 2/3] PCI: microchip: Fix inbound address translation tables config: mips-randconfig-r123-20240626 (https://download.01.org/0day-ci/archive/20240627/202406270503.ZMuH0eTS-lkp@intel.com/config) compiler: mipsel-linux-gcc (GCC) 13.2.0 reproduce: (https://download.01.org/0day-ci/archive/20240627/202406270503.ZMuH0eTS-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202406270503.ZMuH0eTS-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> drivers/pci/controller/pcie-microchip-host.c:1000:60: sparse: sparse: cast truncates bits from constant value (100000000 becomes 0) vim +1000 drivers/pci/controller/pcie-microchip-host.c 961 962 static int mc_pcie_setup_inbound_ranges(struct platform_device *pdev, struct mc_pcie *port) 963 { 964 struct device *dev = &pdev->dev; 965 struct device_node *dn = dev->of_node; 966 struct of_range_parser parser; 967 struct of_range range; 968 int atr_index = 0; 969 970 /* 971 * MPFS PCIe root port is 32-bit only, behind a Fabric Interface 972 * Controller FPGA logic block which contains the AXI-S interface. 973 * 974 * From the point of view of the PCIe root port, There are only 975 * two supported Root Port configurations 976 * 977 * Configuration 1: for use with fully coherent designs; supports a 978 * window from 0x0 (CPU space) to specified PCIe space. 979 * 980 * Configuration 2: for use with non-coherent designs; supports two 981 * 1 Gb wide windows to CPU space; one mapping cpu space 0 to pcie 982 * space 0x80000000 and mapping cpu space 0x40000000 to pcie 983 * space 0xc0000000. This cfg needs two windows because of how 984 * the MSI space is allocated in the AXI-S range on MPFS. 985 * 986 * The FIC interface outside the PCIe block *must* complete the inbound 987 * address translation as per MCHP MPFS FPGA design guidelines. 988 */ 989 if (device_property_read_bool(dev, "dma-noncoherent")) { 990 /* 991 * Always need same two tables in this case. Need two tables 992 * due to hardware interactions between address and size. 993 */ 994 mc_pcie_setup_inbound_atr(0, 0, MPFS_NC_BOUNCE_ADDR, SZ_1G); 995 mc_pcie_setup_inbound_atr(1, SZ_1G, MPFS_NC_BOUNCE_ADDR + SZ_1G, SZ_1G); 996 } else { 997 /* Find any dma-ranges */ 998 if (of_pci_dma_range_parser_init(&parser, dn)) { 999 /* No dma-range property - setup default */ > 1000 mc_pcie_setup_inbound_atr(0, 0, 0, SZ_4G); 1001 return 0; 1002 } 1003 1004 for_each_of_range(&parser, &range) { 1005 if (atr_index >= MC_MAX_NUM_INBOUND_WINDOWS) { 1006 dev_err(dev, "too many inbound ranges; %d available tables\n", 1007 MC_MAX_NUM_INBOUND_WINDOWS); 1008 return -EINVAL; 1009 } 1010 mc_pcie_setup_inbound_atr(atr_index, 0, range.pci_addr, range.size); 1011 atr_index++; 1012 } 1013 } 1014 1015 return 0; 1016 } 1017 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki