From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BEDA0C3064D for ; Tue, 2 Jul 2024 11:47:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=R+Ofa6woHbWPrIniq6hYqo89KID+TX99GpCooXPjX0g=; b=w0WvdQS8gFdEj3b+CW0WBV3UIj 4vLEp2hdptxJoWEndgte7u/4aDztLAf4JOdXVj+M2femn05HRlMkZ0Fj7m6IOLwKRhntpuFC/6RvN DOYEzftehAhWIn1a+3Pko+LXHO3cn9ojeJYFJnj/wE5sPnE16ZEGTyTaRwSyRFze/65fN/S4EwO32 vqjXzLncFok2cjJoGvus8qzPygtDGC+jJ5h+O+4bvk4Dw4NTvPdyw9lqjSkf3o9YX32eejsgc2Nw7 HYVM9HddH5/cDZYsCBmagVjrLnRnT+G/GAdqHHEJwtXT+CAj30F9aotYxlra2Ljul/aveO3quIKbG 84Psi/bg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sObyF-00000006XxI-2TO8; Tue, 02 Jul 2024 11:46:51 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sObvZ-00000006WR8-0xJ4 for linux-arm-kernel@lists.infradead.org; Tue, 02 Jul 2024 11:44:06 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 88DA7CE16FE; Tue, 2 Jul 2024 11:44:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ADEECC4AF0C; Tue, 2 Jul 2024 11:44:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719920642; bh=Yhqn8PgtMd6k88iUg8Ydt6hqL7KAalQ4pH8RtPIMvok=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BNBDy1RSN7iXus6VCtBUzw8xG1dEsrRSozce5yRmNMPJZkrGGduE7pq0sJZkFSG4v yE9+l6TaghRkRHsFbterKCTXNKpzo59yaIXdW7vHmo8Iozs0/z6fEdv5uOVWA4r9X/ jo5AQ0kr+wfV5arquiZS8sCu9NOn2lzEkqg9R5Nw4UeYFLsvQr0fDUhvW8W9+KWdSY 9TMXFBckqa2PgDXyuoeUzekzqdYoRa8W2qbt7YDFElQIrFI7MHFfWB5G98PUzV6HOc jJinkJTyV5x3ALCXg4wwSm5laJErLdr0+u3xjPExq8/IRMw9t6WpDdHQvrUQubkj8K 1zi1llwzdaYBg== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v2 21/30] irqchip/armada-370-xp: Use consistent variable names for hwirqs Date: Tue, 2 Jul 2024 13:42:53 +0200 Message-ID: <20240702114302.22475-22-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240702114302.22475-1-kabel@kernel.org> References: <20240702114302.22475-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240702_044405_674273_B9E55224 X-CRM114-Status: GOOD ( 20.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use consistent variable names for hwirqs: when iterating, use "i", otherwise use "hwirq". Signed-off-by: Marek Behún --- drivers/irqchip/irq-armada-370-xp.c | 56 ++++++++++++++--------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index be1c3721f980..a710a325f81a 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -117,7 +117,7 @@ #define MPIC_SW_TRIG_INT 0x04 #define MPIC_INT_SET_ENABLE 0x30 #define MPIC_INT_CLEAR_ENABLE 0x34 -#define MPIC_INT_SOURCE_CTL(irq) (0x100 + (irq) * 4) +#define MPIC_INT_SOURCE_CTL(hwirq) (0x100 + (hwirq) * 4) #define MPIC_INT_SOURCE_CPU_MASK GENMASK(3, 0) #define MPIC_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << (cpuid)) @@ -199,9 +199,9 @@ static inline unsigned int msi_doorbell_end(void) PCI_MSI_FULL_DOORBELL_END; } -static inline bool mpic_is_percpu_irq(irq_hw_number_t irq) +static inline bool mpic_is_percpu_irq(irq_hw_number_t hwirq) { - return irq <= MPIC_MAX_PER_CPU_IRQS; + return hwirq <= MPIC_MAX_PER_CPU_IRQS; } /* @@ -530,11 +530,11 @@ static void mpic_smp_cpu_init(void) static void mpic_reenable_percpu(void) { /* Re-enable per-CPU interrupts that were enabled before suspend */ - for (unsigned int irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) { + for (unsigned int i = 0; i < MPIC_MAX_PER_CPU_IRQS; i++) { struct irq_data *data; unsigned int virq; - virq = irq_linear_revmap(mpic_domain, irq); + virq = irq_linear_revmap(mpic_domain, i); if (!virq) continue; @@ -586,20 +586,20 @@ static struct irq_chip mpic_irq_chip = { }; static int mpic_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) + irq_hw_number_t hwirq) { /* IRQs 0 and 1 cannot be mapped, they are handled internally */ - if (hw <= 1) + if (hwirq <= 1) return -EINVAL; mpic_irq_mask(irq_get_irq_data(virq)); - if (!mpic_is_percpu_irq(hw)) - writel(hw, per_cpu_int_base + MPIC_INT_CLEAR_MASK); + if (!mpic_is_percpu_irq(hwirq)) + writel(hwirq, per_cpu_int_base + MPIC_INT_CLEAR_MASK); else - writel(hw, main_int_base + MPIC_INT_SET_ENABLE); + writel(hwirq, main_int_base + MPIC_INT_SET_ENABLE); irq_set_status_flags(virq, IRQ_LEVEL); - if (mpic_is_percpu_irq(hw)) { + if (mpic_is_percpu_irq(hwirq)) { irq_set_percpu_devid(virq); irq_set_chip_and_handler(virq, &mpic_irq_chip, handle_percpu_devid_irq); @@ -654,15 +654,15 @@ static inline void mpic_handle_ipi_irq(void) {} static void mpic_handle_cascade_irq(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned long irqmap, irqn, irqsrc, cpuid; + unsigned long irqmap, i, irqsrc, cpuid; chained_irq_enter(chip, desc); irqmap = readl_relaxed(per_cpu_int_base + MPIC_PPI_CAUSE); cpuid = cpu_logical_map(smp_processor_id()); - for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { - irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(irqn)); + for_each_set_bit(i, &irqmap, BITS_PER_LONG) { + irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(i)); /* Check if the interrupt is not masked on current CPU. * Test IRQ (0-1) and FIQ (8-9) mask bits. @@ -670,12 +670,12 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc) if (!(irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid))) continue; - if (irqn == 0 || irqn == 1) { + if (i == 0 || i == 1) { mpic_handle_msi_irq(); continue; } - generic_handle_domain_irq(mpic_domain, irqn); + generic_handle_domain_irq(mpic_domain, i); } chained_irq_exit(chip, desc); @@ -683,26 +683,26 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc) static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs) { - u32 irqstat, irqnr; + u32 irqstat, i; do { irqstat = readl_relaxed(per_cpu_int_base + MPIC_CPU_INTACK); - irqnr = FIELD_GET(MPIC_CPU_INTACK_IID_MASK, irqstat); + i = FIELD_GET(MPIC_CPU_INTACK_IID_MASK, irqstat); - if (irqnr > 1022) + if (i > 1022) break; - if (irqnr > 1) { - generic_handle_domain_irq(mpic_domain, irqnr); + if (i > 1) { + generic_handle_domain_irq(mpic_domain, i); continue; } /* MSI handling */ - if (irqnr == 1) + if (i == 1) mpic_handle_msi_irq(); /* IPI Handling */ - if (irqnr == 0) + if (i == 0) mpic_handle_ipi_irq(); } while (1); } @@ -719,24 +719,24 @@ static void mpic_resume(void) bool src0, src1; /* Re-enable interrupts */ - for (irq_hw_number_t irq = 0; irq < mpic_domain->hwirq_max; irq++) { + for (irq_hw_number_t i = 0; i < mpic_domain->hwirq_max; i++) { struct irq_data *data; unsigned int virq; - virq = irq_linear_revmap(mpic_domain, irq); + virq = irq_linear_revmap(mpic_domain, i); if (!virq) continue; data = irq_get_irq_data(virq); - if (!mpic_is_percpu_irq(irq)) { + if (!mpic_is_percpu_irq(i)) { /* Non per-CPU interrupts */ - writel(irq, per_cpu_int_base + MPIC_INT_CLEAR_MASK); + writel(i, per_cpu_int_base + MPIC_INT_CLEAR_MASK); if (!irqd_irq_disabled(data)) mpic_irq_unmask(data); } else { /* Per-CPU interrupts */ - writel(irq, main_int_base + MPIC_INT_SET_ENABLE); + writel(i, main_int_base + MPIC_INT_SET_ENABLE); /* * Re-enable on the current CPU, mpic_reenable_percpu() -- 2.44.2