All of lore.kernel.org
 help / color / mirror / Atom feed
From: kernel test robot <lkp@intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: oe-kbuild-all@lists.linux.dev
Subject: [jgunthorpe:iommu_pt 37/53] drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:37: warning: "VA_BITS" redefined
Date: Thu, 4 Jul 2024 18:45:34 +0800	[thread overview]
Message-ID: <202407041854.qownApOL-lkp@intel.com> (raw)

tree:   https://github.com/jgunthorpe/linux iommu_pt
head:   2bf23486e7eae67485953abf3529ad2d3a90384b
commit: 23dbb9b1e1ec4cc15b44eeb954b5045ed86daf78 [37/53] add COMPILE_TEST
config: loongarch-allyesconfig (https://download.01.org/0day-ci/archive/20240704/202407041854.qownApOL-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240704/202407041854.qownApOL-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202407041854.qownApOL-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:32:
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h:755:41: error: field 'mmu_notifier' has incomplete type
     755 |         struct mmu_notifier             mmu_notifier;
         |                                         ^~~~~~~~~~~~
>> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:37: warning: "VA_BITS" redefined
      37 | #define VA_BITS 39
         | 
   In file included from arch/loongarch/include/asm/uaccess.h:17,
                    from include/linux/uaccess.h:11,
                    from include/linux/sched/task.h:13,
                    from include/linux/sched/signal.h:9,
                    from include/linux/rcuwait.h:6,
                    from include/linux/percpu-rwsem.h:7,
                    from include/linux/fs.h:33,
                    from arch/loongarch/include/asm/elf.h:9,
                    from include/linux/elf.h:6,
                    from include/linux/module.h:19,
                    from include/linux/device/driver.h:21,
                    from include/linux/device.h:32,
                    from include/linux/acpi.h:14,
                    from drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:12:
   arch/loongarch/include/asm/pgtable.h:45: note: this is the location of the previous definition
      45 | #define VA_BITS         (PGDIR_SHIFT + (PAGE_SHIFT - 3))
         | 


vim +/VA_BITS +37 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

    31	
  > 32	#include "arm-smmu-v3.h"
    33	#include "../../dma-iommu.h"
    34	
    35	#ifndef __aarch64__
    36	#define wfe()
  > 37	#define VA_BITS 39
    38	#define cpus_have_cap(x) false
    39	#endif
    40	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

                 reply	other threads:[~2024-07-04 10:46 UTC|newest]

Thread overview: [no followups] expand[flat|nested]  mbox.gz  Atom feed

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=202407041854.qownApOL-lkp@intel.com \
    --to=lkp@intel.com \
    --cc=jgg@nvidia.com \
    --cc=oe-kbuild-all@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.