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[142.68.80.239]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6b61ba77767sm35416846d6.95.2024.07.12.06.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 06:53:26 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1sSGiE-000Slh-6n; Fri, 12 Jul 2024 10:53:26 -0300 Date: Fri, 12 Jul 2024 10:53:26 -0300 From: Jason Gunthorpe To: Robin Murphy Cc: Yi Liu , Vasant Hegde , Joerg Roedel , "iommu@lists.linux.dev" , Suravee Suthikulpanit , Will Deacon , Baolu Lu Subject: Re: [RFC] iommu_ops->domain_alloc_paging() enhancement to support AMD IOMMU driver Message-ID: <20240712135326.GD14050@ziepe.ca> References: <26524622-971f-47f5-936e-d0173d342288@amd.com> <1f8f04e5-3b70-45de-bd93-e3c96fb0a555@amd.com> <68d300af-4d3d-497e-9338-d99dbf88dd21@amd.com> <8bfc6cb7-d2d7-4d4c-9970-f4f207fb54b4@intel.com> <20240709182303.GK14050@ziepe.ca> <3eff5c86-8b5d-491a-955e-794198350ec3@intel.com> <20240711234917.GW14050@ziepe.ca> <35ff9f32-ae60-4124-9ced-42f82c2b4f93@arm.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35ff9f32-ae60-4124-9ced-42f82c2b4f93@arm.com> On Fri, Jul 12, 2024 at 02:40:37PM +0100, Robin Murphy wrote: > > > BTW. SVA domain shall not be attached to RID I suppose. This should > > > be a common restriction across vendors. Do you think it is valuable > > > to let iommu core block such an attempt? > > > > Yeah, maybe. > > There's no functional reason to disallow it for Arm SMMUs, at least, so it's > something that could potentially want relaxing back to per-driver in > future. I think everyone can technically do SVA as everyone should be able to do PRI on the RID. We want PRI on RID anyhow for unpinned guest KVM support someday. My specific "maybe" was because SVA is troublesome for MSI, on ARM we won't have an ITS page mapped for instance. > I've heard murmurings over the years about potential use-cases for SVA with > platform and/or non-PASID PCI devices, but never anything concrete for > existing hardware. I imagine we can expect to see more SVA-interested > on-chip accelerators in future, but whether they'll all be nice and support > Substreams (i.e. "platform PASIDs") is the question... So I guess they don't send MSI down those special stream ids? It makes sense as a use case to me. Thanks, Jason