Re: [PATCH 0/2] spi: sunxi: Improve the loading speed

[Andre Przywara <andre.przywara@arm.com>]

On Fri, 12 Jul 2024 18:28:15 +0100
Peter Robinson <pbrobinson@gmail.com> wrote:

> On Fri, 12 Jul 2024 at 18:25, Michael Walle <mwalle@kernel.org> wrote:
> >
> > Right now, the maximal transfer speed from an SPI flash on a V3s is
> > about 240kb/s. That is pretty slow. It turns out, that due to an
> > error u-boot is setting the maximum frequency to 1MHz. By fixing
> > that another bug is unearthed: one cannot set a clock divider of 1:1
> > due to the handling between CDR1 and CDR2 handling. By fixing that
> > I achieved loading speeds of about 1.5MB/s.  
> 
> Minor nit, should the clock fix go first so there's not a regression
> if someone needs to do a bisect on the first commit?

I am not sure this really matters here, since this patch just lifts the
frequency from 12 MHz to 24 MHz, while patch 1/2 lifts it from 1 MHz to
12 MHz. So there is no regression as such.

Cheers,
Andre

> 
> > Michael Walle (2):
> >   spi: sunxi: drop max_hz handling
> >   spi: sunxi: fix clock divider calculation for max frequency setting
> >
> >  drivers/spi/spi-sunxi.c | 28 +++++++++++++++-------------
> >  1 file changed, 15 insertions(+), 13 deletions(-)
> >
> > --
> > 2.39.2
> >