From: Raghavendra Rao Ananta <rananta@google.com>
To: Oliver Upton <oliver.upton@linux.dev>,
Marc Zyngier <maz@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>
Cc: Raghavendra Rao Anata <rananta@google.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: [PATCH] arm64/sysreg: Correct the values for GICv4.1
Date: Thu, 18 Jul 2024 21:55:32 +0000 [thread overview]
Message-ID: <20240718215532.616447-1-rananta@google.com> (raw)
Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
Hence, correct them to reflect ARM ARM.
Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
---
arch/arm64/tools/sysreg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a4c1dd4741a47..7ceaa1e0b4bc2 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -149,7 +149,7 @@ Res0 63:32
UnsignedEnum 31:28 GIC
0b0000 NI
0b0001 GICv3
- 0b0010 GICv4p1
+ 0b0011 GICv4p1
EndEnum
UnsignedEnum 27:24 Virt_frac
0b0000 NI
@@ -903,7 +903,7 @@ EndEnum
UnsignedEnum 27:24 GIC
0b0000 NI
0b0001 IMP
- 0b0010 V4P1
+ 0b0011 V4P1
EndEnum
SignedEnum 23:20 AdvSIMD
0b0000 IMP
base-commit: 0c3836482481200ead7b416ca80c68a29cfdaabd
--
2.45.2.1089.g2a221341d9-goog
next reply other threads:[~2024-07-18 21:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-18 21:55 Raghavendra Rao Ananta [this message]
2024-07-19 7:55 ` [PATCH] arm64/sysreg: Correct the values for GICv4.1 Marc Zyngier
2024-07-22 8:00 ` Anshuman Khandual
2024-07-21 9:29 ` Zenghui Yu
2024-07-22 8:37 ` Anshuman Khandual
2024-07-22 8:39 ` Anshuman Khandual
2024-07-23 15:46 ` Will Deacon
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