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[185.176.79.56]) by mx.google.com with ESMTPS id 41be03b00d2f7-7a1de0ea145si3016847a12.808.2024.07.22.05.54.47 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Jul 2024 05:54:47 -0700 (PDT) Received-SPF: pass (google.com: domain of jonathan.cameron@huawei.com designates 185.176.79.56 as permitted sender) client-ip=185.176.79.56; Authentication-Results: mx.google.com; spf=pass (google.com: domain of jonathan.cameron@huawei.com designates 185.176.79.56 as permitted sender) smtp.mailfrom=jonathan.cameron@huawei.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4WSKtv6yHtz6K61X; Mon, 22 Jul 2024 20:52:39 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (unknown [7.191.163.240]) by mail.maildlp.com (Postfix) with ESMTPS id 798FC140D1A; Mon, 22 Jul 2024 20:54:43 +0800 (CST) Received: from localhost (10.203.174.77) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 22 Jul 2024 13:54:42 +0100 Date: Mon, 22 Jul 2024 13:54:42 +0100 From: Jonathan Cameron To: Zhao Liu CC: "Daniel P .\" =?ISO-8859-1?Q?Berrang=E9?= , Eduardo Habkost , Marcel Apfelbaum , Philippe =?ISO-8859-1?Q?Mathieu-Daud=E9?= , Yanan Wang , Michael S.Tsirkin , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , Alex =?ISO-8859-1?Q?Benn=E9e?= , Peter Maydell , Sia Jee Heng , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma "@domain.invalid Subject: Re: [PATCH 0/8] Introduce SMP Cache Topology Message-ID: <20240722135442.000003de@Huawei.com> In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.174.77] X-ClientProxiedBy: lhrpeml500002.china.huawei.com (7.191.160.78) To lhrpeml500005.china.huawei.com (7.191.163.240) X-TUID: kH9VjGLafxsp On Thu, 4 Jul 2024 11:15:55 +0800 Zhao Liu wrote: > Hi all, > > Since the previous RFC v2, I've reimplemented smp-cache object based on > Daniel's comment (thanks Daniel!), which is both flexible to support > current cache topology requirements and extensible. > > So, I officially convert the RFC to PATCH. > > Background on smp cache topology can be found in the previous RFC v2 > cover letter: > > https://lore.kernel.org/qemu-devel/20240530101539.768484-1-zhao1.liu@intel.com/ > > The following content focuses on this series implementation of the > smp-cache object. > Hi Zhao Liu I've not commented on most of the x86 specific corners, but we are working on arm64 / PPTT support combining the info form CPU registers with the 'where' description this provides. Should have a series on top of your work to post soon. To me the interface looks fairly clean so I hope this object approach works for everyone! Jonathan