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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Haibo Xu , Atish Kumar Patra , Drew Fustini , Sunil V L Subject: [PATCH v7 00/17] RISC-V: ACPI: Add external interrupt controller support Date: Mon, 29 Jul 2024 19:52:22 +0530 Message-ID: <20240729142241.733357-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This series adds support for the below ECR approved by ASWG. 1) MADT - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing The series primarily enables irqchip drivers for RISC-V ACPI based platforms. The series can be broadly categorized like below. 1) PCI ACPI related functions are migrated from arm64 to common file so that we don't need to duplicate them for RISC-V. 2) Added support for re-ordering the probe of interrupt controllers when IRQCHIP_ACPI_DECLARE is used. 3) To ensure probe order between interrupt controllers and devices, implicit dependency is created similar to when _DEP is present. 4) ACPI support added in RISC-V interrupt controller drivers. Changes since v6: 1) Update to commit message/code comments as per feedback from Bjorn. 2) Rebased to 6.11-rc1. Changes since v5: 1) Addressed feedback from Thomas. 2) Created separate patch for refactoring DT code in IMSIC 3) Separated a fix in riscv-intc irqchip driver and sent separately. This series depends on that patch [1]. 4) Dropped serial driver patch since it depends on Andy's refactoring series [2]. RISC-V patches will be sent separately later once Andy series get accepted. 5) Rebased to v6.10-rc1 which has AIA DT patches. 6) Updated tags. Changes since RFC v4: 1) Removed RFC tag as the RFCv4 design looked reasonable. 2) Dropped PCI patch needed to avoid warning when there is no MSI controller. This will be sent later separately after the current series. 3) Dropped PNP handling of _DEP since there is new ACPI ID for generic 16550 UART. Added the serial driver patch instead. 4) Rebased to latest linux-next. 5) Reordered/squashed patches in the series Changes since RFC v3: 1) Moved to _DEP method instead of fw_devlink. 2) PLIC/APLIC driver probe using namespace devices. 3) Handling PNP devices as part of clearing dependency. 4) Rebased to latest linux-next to get AIA DT drivers. Changes since RFC v2: 1) Introduced fw_devlink for ACPI nodes for IRQ dependency. 2) Dropped patches in drivers which are not required due to fw_devlink support. 3) Dropped pci_set_msi() patch and added a patch in pci_create_root_bus(). 4) Updated pnp_irq() patch so that none of the actual PNP drivers need to change. Changes since RFC v1: 1) Abandoned swnode approach as per Marc's feedback. 2) To cope up with AIA series changes which changed irqchip driver probe from core_initcall() to platform_driver, added patches to support deferred probing. 3) Rebased on top of Anup's AIA v11 and added tags. To test the series, 1) qemu should be built using the latest master branch. 2) EDK2 should be built using the instructions at: https://github.com/tianocore/edk2/blob/master/OvmfPkg/RiscVVirt/README.md NOTE: One should be able to use u-boot as well as per instructions from Björn. https://lore.kernel.org/lkml/87a5lqsrvh.fsf@all.your.base.are.belong.to.us/ 3) Build Linux using this series. Since serial driver patch is dropped, SBI_HVC console needs to be used. Enable below configs while building the linux. CONFIG_NONPORTABLE=y CONFIG_HVC_RISCV_SBI=y Run Qemu: qemu-system-riscv64 \ -M virt,pflash0=pflash0,pflash1=pflash1,aia=aplic-imsic \ -m 2G -smp 8 \ -serial mon:stdio \ -device virtio-gpu-pci -full-screen \ -device qemu-xhci \ -device usb-kbd \ -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \ -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \ -netdev user,id=net0 -device virtio-net-pci,netdev=net0 \ -kernel arch/riscv/boot/Image \ -initrd rootfs.cpio \ -append "root=/dev/ram ro console=hvc0 rootwait earlycon=sbi" To boot with APLIC only, use aia=aplic. To boot with PLIC, remove aia= option. This series is also available in acpi_b2_v7 branch at https://github.com/vlsunil/linux.git [2] - https://lore.kernel.org/lkml/20240506140308.4040735-1-andriy.shevchenko@linux.intel.com/ Sunil V L (17): arm64: PCI: Migrate ACPI related functions to pci-acpi.c ACPI: scan: Add a weak function to reorder the IRQCHIP probe ACPI: bus: Add acpi_riscv_init function ACPI: scan: Refactor dependency creation ACPI: scan: Add RISC-V interrupt controllers to honor list ACPI: scan: Define weak function to populate dependencies ACPI: bus: Add RINTC IRQ model for RISC-V ACPI: pci_link: Clear the dependencies after probe ACPI: RISC-V: Implement PCI related functionality ACPI: RISC-V: Implement function to reorder irqchip probe entries ACPI: RISC-V: Initialize GSI mapping structures ACPI: RISC-V: Implement function to add implicit dependencies irqchip/riscv-intc: Add ACPI support for AIA irqchip/riscv-imsic-state: Create separate function for DT irqchip/riscv-imsic: Add ACPI support irqchip/riscv-aplic: Add ACPI support irqchip/sifive-plic: Add ACPI support arch/arm64/kernel/pci.c | 191 ------------ arch/riscv/Kconfig | 2 + arch/riscv/include/asm/irq.h | 55 ++++ arch/riscv/kernel/acpi.c | 33 +- drivers/acpi/bus.c | 4 + drivers/acpi/pci_link.c | 2 + drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/init.c | 14 + drivers/acpi/riscv/init.h | 4 + drivers/acpi/riscv/irq.c | 335 +++++++++++++++++++++ drivers/acpi/scan.c | 103 ++++--- drivers/irqchip/irq-riscv-aplic-direct.c | 22 +- drivers/irqchip/irq-riscv-aplic-main.c | 69 +++-- drivers/irqchip/irq-riscv-aplic-main.h | 1 + drivers/irqchip/irq-riscv-aplic-msi.c | 9 +- drivers/irqchip/irq-riscv-imsic-early.c | 64 +++- drivers/irqchip/irq-riscv-imsic-platform.c | 32 +- drivers/irqchip/irq-riscv-imsic-state.c | 160 +++++----- drivers/irqchip/irq-riscv-imsic-state.h | 2 +- drivers/irqchip/irq-riscv-intc.c | 90 ++++++ drivers/irqchip/irq-sifive-plic.c | 94 ++++-- drivers/pci/pci-acpi.c | 182 +++++++++++ include/acpi/acpi_bus.h | 2 + include/linux/acpi.h | 9 + include/linux/irqchip/riscv-imsic.h | 9 + 25 files changed, 1113 insertions(+), 377 deletions(-) create mode 100644 drivers/acpi/riscv/init.c create mode 100644 drivers/acpi/riscv/init.h create mode 100644 drivers/acpi/riscv/irq.c -- 2.43.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B8BEC3DA61 for ; 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Wysocki" , Catalin Marinas , Atish Kumar Patra , Robert Moore , Samuel Holland , Conor Dooley , Palmer Dabbelt , Drew Fustini , Anup Patel , Bjorn Helgaas , Thomas Gleixner , Andrew Jones , Will Deacon , Len Brown Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org VGhpcyBzZXJpZXMgYWRkcyBzdXBwb3J0IGZvciB0aGUgYmVsb3cgRUNSIGFwcHJvdmVkIGJ5IEFT V0cuCjEpIE1BRFQgLSBodHRwczovL2RyaXZlLmdvb2dsZS5jb20vZmlsZS9kLzFvTUdQeU9ENThK YVBnTWwxcEthc1QtVktzSUtpYTd6Ui92aWV3P3VzcD1zaGFyaW5nCgpUaGUgc2VyaWVzIHByaW1h cmlseSBlbmFibGVzIGlycWNoaXAgZHJpdmVycyBmb3IgUklTQy1WIEFDUEkgYmFzZWQKcGxhdGZv cm1zLgoKVGhlIHNlcmllcyBjYW4gYmUgYnJvYWRseSBjYXRlZ29yaXplZCBsaWtlIGJlbG93LiAK CjEpIFBDSSBBQ1BJIHJlbGF0ZWQgZnVuY3Rpb25zIGFyZSBtaWdyYXRlZCBmcm9tIGFybTY0IHRv IGNvbW1vbiBmaWxlIHNvCnRoYXQgd2UgZG9uJ3QgbmVlZCB0byBkdXBsaWNhdGUgdGhlbSBmb3Ig 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