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Tsirkin" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Aurelien Jarno Subject: Re: [PATCH-for-9.1] hw/pci-host/gt64120: Set PCI base address register write mask Message-ID: <20240801062148-mutt-send-email-mst@kernel.org> References: <20240801091332.49256-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240801091332.49256-1-philmd@linaro.org> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.126, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Aug 01, 2024 at 11:13:32AM +0200, Philippe Mathieu-Daudé wrote: > When booting Linux we see: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) > > This is due to missing base address register write mask. > Add it to get: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] > pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] > pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] > pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] > pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] > pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] > > Mention the datasheet referenced. Remove the "Malta assumptions ahead" > comment since the reset values from the datasheet are used. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/pci-host/gt64120.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c > index e02efc9e2e..0b00e98e0a 100644 > --- a/hw/pci-host/gt64120.c > +++ b/hw/pci-host/gt64120.c > @@ -1,6 +1,8 @@ > /* > * QEMU GT64120 PCI host > * > + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) > + * > * Copyright (c) 2006,2007 Aurelien Jarno > * > * Permission is hereby granted, free of charge, to any person obtaining a copy > @@ -1213,17 +1215,28 @@ static void gt64120_realize(DeviceState *dev, Error **errp) > > static void gt64120_pci_realize(PCIDevice *d, Error **errp) > { > - /* FIXME: Malta specific hw assumptions ahead */ > + > + /* Values from chapter 17.16 "PCI Configuration" */ > + > pci_set_word(d->config + PCI_COMMAND, 0); > pci_set_word(d->config + PCI_STATUS, > PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); > pci_config_set_prog_interface(d->config, 0); > + > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff009); > + If you make these writeable, then you should set them on reset, as opposed to unrealize. > pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); > pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); > pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); > pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); > pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); > pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); > + > pci_set_byte(d->config + 0x3d, 0x01); > } > > -- > 2.45.2