From mboxrd@z Thu Jan 1 00:00:00 1970 Received: by 2002:a17:505:1e8b:b0:1be9:327d:8ee3 with SMTP id mw11csp986360njb; Mon, 5 Aug 2024 13:17:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUplSb150XgC2LDFzb/Pc69alQSFVZkMz7rK8Y9hW5ZCWzHC/icx1wbRSULYoVaSQ8JI/c7fkVU2VLGFRfq/h7oVcJWXf2u X-Received: by 2002:a05:6902:2190:b0:e0b:acc7:b206 with SMTP id 3f1490d57ef6-e0bde26456amr11459190276.8.1722889048535; Mon, 05 Aug 2024 13:17:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722889048; cv=none; d=google.com; s=arc-20160816; b=GgDSyQiTMGlyuJJQuj/LRCQH3PfGLlPc6Kcp0WJkTCzlRlYiyE2UMyEsLjmcZx1mt4 Ju//c+H3JQDn0FzrOFzD0AmilSfcyPyl1gpLBvy3l4ewEeASGXxVsWt9cNNyALKH78+q LtmH8EamQuQiqyokrITEcurnqn+MzBDRUhXBwRkODQCJRxhFs+ZonRvjXR/ut+vlDiLe sCVgs8kBpqUIKmEMUyUW6xAgvaRDqkSnYH4H701rlt3mR9b5LY2Q8dm8d3AlG/kS3Oqp YItCegbdfkRRBGkoy59rYRiYmaLPghtfBFODP729lhcw1MaBR5gWH6ZkS4W7xOuqaqjE qpww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:dkim-signature; bh=4wdCCjeNwO8Nd9IfMEbL3mdHNd1GL/ZDoT8770kOdC0=; fh=krvzf6IQExm3y/HzKeN79mOPFzgGuur4WEAty6iIdNo=; b=Fc3QRBoXzZLDpHnUZJH1RK2PJtIPiycAhSTEyAIfT8Ye8RanmPoCxvuFmxGi/Ryi5v jhjQJ/K6qg9yhupOtaW2K8meMG7aZ9fBwhvZlsT9jZlEPxbhzHglNopM14A1PHjjAbHo WyNoVMOHrgFNI+6qTXSTHv8Z+QPTzUHKdYiPh6VMFqZAwdoD3hOoqQPP01SepyBEhv4Z XY6FOa1I0I3H41/pVpmEEnNmo5nQLI4acJv/CUq9tvOk3orlW88PRfxIxuD4ohFZQdYm rwfBlukw2nt7O2LMv7w7IqvOrbKkW8BOFqKWwkNXoSv+eUVr5uBCEFGIv+7lAbMHKDrL 1TjQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=JwCZl1OL; spf=pass (google.com: domain of 3wdoxzgukc78yf0nulttlqj.htrfqj2.gjssjjqnsfwt.twl@flex--tavip.bounces.google.com designates 209.85.220.73 as permitted sender) smtp.mailfrom=3WDOxZgUKC78yf0nulttlqj.htrfqj2.gjssjjqnsfwt.twl@flex--tavip.bounces.google.com; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com; dara=neutral header.i=@linaro.org Return-Path: <3WDOxZgUKC78yf0nulttlqj.htrfqj2.gjssjjqnsfwt.twl@flex--tavip.bounces.google.com> Received: from mail-sor-f73.google.com (mail-sor-f73.google.com. [209.85.220.73]) by mx.google.com with SMTPS id 3f1490d57ef6-e0be533b619sor4825062276.4.2024.08.05.13.17.28 for (Google Transport Security); Mon, 05 Aug 2024 13:17:28 -0700 (PDT) Received-SPF: pass (google.com: domain of 3wdoxzgukc78yf0nulttlqj.htrfqj2.gjssjjqnsfwt.twl@flex--tavip.bounces.google.com designates 209.85.220.73 as permitted sender) client-ip=209.85.220.73; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=JwCZl1OL; spf=pass (google.com: domain of 3wdoxzgukc78yf0nulttlqj.htrfqj2.gjssjjqnsfwt.twl@flex--tavip.bounces.google.com designates 209.85.220.73 as permitted sender) smtp.mailfrom=3WDOxZgUKC78yf0nulttlqj.htrfqj2.gjssjjqnsfwt.twl@flex--tavip.bounces.google.com; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com; dara=neutral header.i=@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1722889048; x=1723493848; darn=linaro.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=4wdCCjeNwO8Nd9IfMEbL3mdHNd1GL/ZDoT8770kOdC0=; b=JwCZl1OLblXdSULxilw6SapftHElOTkdlePB4EIdH8rEpV3odjP8yWGc1Y/ABBEeet gjHyG2BPsAwPUFdSliWPqw0hnaXlnJl9l9NQbgSDIPq1jBEXLJs75pK9eCGSzc2LfEp8 OMJehFFFeRlpYl86qk5XwwF/TWN9xgUd/73o1GwWMmrn+8LelPsJqRH2sUj6k5M1KVkC ZsXprOpXkP40COAlko16LSp/yLndCgd5hjDZ9tzwsOvVxOhe9MpWgxFAtecm5A9BIA0U PcfDQK+L98GvNc76SckmRjRVHdT2w6cb0zYQ7KyU12Ar61lX/yk22nsY5exMqEaANMj/ wkvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722889048; x=1723493848; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=4wdCCjeNwO8Nd9IfMEbL3mdHNd1GL/ZDoT8770kOdC0=; b=stICj5/j6317yjZzMB/xV7qVD3WbSSyN8vAHEeeDgUJ9BN+d7EDMWSJBjgfkLbhTtu ztJXm47DTyyszxrWIvbGU+vwxzVF0B2TQtxnQJF9lSoxL/c+Mwyp2JQgW7oTU1oiGSoi QXiUKxSQhPPi/R9tcV6TAq1n0RoZzxpiOSCtdmxjgGagOpsNH4pNboughVl/Zt2UmjBh z1BI49JEUbHKXSCu0hnMjqHVf+7tWMadRQ/Wkb3bbxVpVNX8J3x0MbWoa8itl05Z1ijl opiHAwcxg5W/U91Vd7kFQGtyel3V21EX83v5dKpekk40nGAREm0a5Y+KMlrnur8p8kAZ s0ZA== X-Forwarded-Encrypted: i=1; AJvYcCVe8BtPu8ooskJgl1ST1gV7dolfVxzQ4BcSrdYeNKKQxrXTFvjYfE5Zbh9Zz+iqtKpBCJdRplykIVB+oQ+MkPAVJVRqBhUQ X-Gm-Message-State: AOJu0Yz/fGU3/6s7mFeKlbSDNqwYKqaYlexNV1QVk9hkKr0ZiG8fWvi8 tl8sPKrQ1QPFGETB2098tr4clt1BJzKGs0pnWPLg/Otm5klq8eXhK4B/MeSCe+LauuPdbwrSvQ= = X-Google-Smtp-Source: AGHT+IFc6T3TAxrL7s5Lv7ug2GUJd5MzzOoyezk2KKzPhvbVP98dIUt1LyxRK3Igl2effMsOknmdhYg5+A== X-Received: from warp10.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:750]) (user=tavip job=sendgmr) by 2002:a05:6902:709:b0:e0b:9412:3295 with SMTP id 3f1490d57ef6-e0bde1eaf4bmr23833276.3.1722889048127; Mon, 05 Aug 2024 13:17:28 -0700 (PDT) Date: Mon, 5 Aug 2024 13:16:59 -0700 In-Reply-To: <20240805201719.2345596-1-tavip@google.com> Mime-Version: 1.0 References: <20240805201719.2345596-1-tavip@google.com> X-Mailer: git-send-email 2.46.0.rc2.264.g509ed76dc8-goog Message-ID: <20240805201719.2345596-5-tavip@google.com> Subject: [RFC PATCH 04/23] hw/arm: add SVD file for NXP i.MX RT595 From: Octavian Purdila To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, stefanst@google.com, pbonzini@redhat.com, alex.bennee@linaro.org, thuth@redhat.com, peter.maydell@linaro.org, marcandre.lureau@redhat.com, alistair@alistair23.me, berrange@redhat.com, philmd@linaro.org, jsnow@redhat.com, crosa@redhat.com, bleal@redhat.com Content-Type: text/plain; charset="UTF-8" X-TUID: HR7g62QsREtU Picked from: https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml NOTE: the file is truncated to keep the email size reasonable. Please use the link above and download the full file if you want to try out the patch. Signed-off-by: Octavian Purdila --- hw/arm/svd/MIMXRT595S_cm33.xml | 224052 ++++++++++++++++++++++++++++++ 1 file changed, 224052 insertions(+) create mode 100644 hw/arm/svd/MIMXRT595S_cm33.xml diff --git a/hw/arm/svd/MIMXRT595S_cm33.xml b/hw/arm/svd/MIMXRT595S_cm33.xml new file mode 100644 index 0000000000..8943aa3555 --- /dev/null +++ b/hw/arm/svd/MIMXRT595S_cm33.xml @@ -0,0 +1,1725 @@ + + + nxp.com + MIMXRT595S_cm33 + 1.0 + MIMXRT595SFAWC,MIMXRT595SFFOC + +Copyright 2016-2023 NXP +SPDX-License-Identifier: BSD-3-Clause + + + CM33 + r2p0 + little + true + true + true + 3 + false + + 8 + 32 + + + RSTCTL0 + Reset Controller 0 + RSTCTL0 + 0x40000000 + + 0 + 0x7C + registers + + + + SYSRSTSTAT + System Reset Status Register + 0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + VDD_POR + VDD CORE Power-On Reset (POR) was detected + 0 + 1 + read-write + + + VDD_POR_EVENT_IS_NOT_DETECTED + No VDD CORE POR event is detected + 0 + + + VDD_POR_EVENT_WAS_DETECTED + VDD CORE POR event was detected + 0x1 + + + + + PAD_RESET + RESETN pin reset was detected + 4 + 1 + read-write + + + PAD_RESET_IS_NOT_DETECTED + No RESETN pin event is detected + 0 + + + PAD_RESET_WAS_DETECTED + RESETN pin event was detected. Write '1' to clear this bit + 0x1 + + + + + ARM_RESET + ARM reset was detected + 5 + 1 + read-write + + + ARM_RESET_IS_NOT_DETECTED + No ARM reset event is detected + 0 + + + ARM_RESET_WAS_DETECTED + ARM reset was detected. Write '1' to clear this bit + 0x1 + + + + + WDT0_RESET + WatchDog Timer 0 reset was detected + 6 + 1 + read-write + + + WDT0_RESET_IS_NOT_DETECTED + No WDT0 reset event detected + 0 + + + WDT0_RESET_WAS_DETECTED + WDT0 reset event detected. Write '1' to clear this bit + 0x1 + + + + + WDT1_RESET + WatchDog Timer 1 reset was detected + 7 + 1 + read-write + + + WDT1_RESET_IS_NOT_DETECTED + No WDT1 reset event detected + 0 + + + WDT1_RESET_WAS_DETECTED + WDT1 reset event detected. Write '1' to clear this bit + 0x1 + + + + + + + PRSTCTL0 + Peripheral Reset Control Register 0 + 0x10 + 32 + read-write + 0x7DF51F0A + 0xFFFFFFFF + + + DSP + Fusion F1 DSP reset control + 1 + 1 + read-write + + + DSP_CLR + Clear Reset + 0 + + + DSP_SET + Set Reset + 0x1 + + + + + AXI_SWITCH + AXI Switch reset control + 3 + 1 + read-write + + + AXI_SWITCH_CLR + Clear Reset + 0 + + + AXI_SWITCH_SET + Set Reset + 0x1 + + + + + POWERQUAD + POWERQUAD reset control + 8 + 1 + read-write + + + POWERQUAD_CLR + Clear Reset + 0 + + + POWERQUAD_SET + Set Reset + 0x1 + + + + + CASPER + CASPER reset control + 9 + 1 + read-write + + + CASPER_CLR + Clear Reset + 0 + + + CASPER_SET + Set Reset + 0x1 + + + + + HASHCRYPT + Hash-Crypt reset control + 10 + 1 + read-write + + + HASHCRYPT_CLR + Clear Reset + 0 + + + HASHCRYPT_SET + Set Reset + 0x1 + + + + + PUF + PUF reset control + 11 + 1 + read-write + + + PUF_CLR + Clear Reset + 0 + + + PUF_SET + Set Reset + 0x1 + + + + + RNG + RNG reset control + 12 + 1 + read-write + + + RNG_CLR + Clear Reset + 0 + + + RNG_SET + Set Reset + 0x1 + + + + + FLEXSPI0_OTFAD + FLEXSPI0 and OTFAD reset control + 16 + 1 + read-write + + + FLEXSPI0_OTFAD_CLR + Clear Reset + 0 + + + FLEXSPI0_OTFAD_SET + Set Reset + 0x1 + + + + + FLEXSPI1 + FLEXSPI1 reset control + 18 + 1 + read-write + + + FLEXSPI1_CLR + Clear Reset + 0 + + + FLEXSPI1_SET + Set Reset + 0x1 + + + + + USBHS_PHY + USB PHY reset control + 20 + 1 + read-write + + + USBHS_PHY_CLR + Clear Reset + 0 + + + USBHS_PHY_SET + Set Reset + 0x1 + + + + + USBHS_DEVICE + USB HS Device reset control + 21 + 1 + read-write + + + USBHS_DEVICE_CLR + Clear Reset + 0 + + + USBHS_DEVICE_SET + Set Reset + 0x1 + + + + + USBHS_HOST + USB HOST reset control + 22 + 1 + read-write + + + USBHS_HOST_CLR + Clear Reset + 0 + + + USBHS_HOST_SET + Set Reset + 0x1 + + + + + USBHS_SRAM + USB RAM reset control + 23 + 1 + read-write + + + USBHS_SRAM_CLR + Clear Reset + 0 + + + USBHS_SRAM_SET + Set Reset + 0x1 + + + + + SCT + SCTimer reset control + 24 + 1 + read-write + + + SCT_CLR + Clear Reset + 0 + + + SCT_SET + Set Reset + 0x1 + + + + + GPU + GPU reset control + 26 + 1 + read-write + + + GPU_CLR + Clear Reset + 0 + + + GPU_SET + Set Reset + 0x1 + + + + + DISPLAY_CONTROLLER + LCDIF Display Controller reset control + 27 + 1 + read-write + + + DISPLAY_CONTROLLER_CLR + Clear Reset + 0 + + + DISPLAY_CONTROLLER_SET + Set Reset + 0x1 + + + + + MIPI_DSI_CONTROLLER + MIPI Digital serial Interface controller reset control + 28 + 1 + read-write + + + MIPI_DSI_CONTROLLER_CLR + Clear Reset + 0 + + + MIPI_DSI_CONTROLLER_SET + Set Reset + 0x1 + + + + + MIPI_DSI_PHY + MIPI DSI PHY reset control + 29 + 1 + read-write + + + MIPI_DSI_PHY_CLR + Clear Reset + 0 + + + MIPI_DSI_PHY_SET + Set Reset + 0x1 + + + + + SMARTDMA + SMARTDMA Event/Algorithm handler reset control + 30 + 1 + read-write + + + SMARTDMA_CLR + Clear Reset + 0 + + + SMARTDMA_SET + Set Reset + 0x1 + + + + + + + PRSTCTL1 + Peripheral Reset Control Register 1 + 0x14 + 32 + read-write + 0x101800C + 0xFFFFFFFF + + + SDIO0 + SDIO0 reset control + 2 + 1 + read-write + + + SDIO0_CLR + Clear Reset + 0 + + + SDIO0_SET + Set Reset + 0x1 + + + + + SDIO1 + SDIO1 reset control + 3 + 1 + read-write + + + SDIO1_CLR + Clear Reset + 0 + + + SDIO1_SET + Set Reset + 0x1 + + + + + ACMP0 + Analog comparator reset control + 15 + 1 + read-write + + + ACMP0_CLR + Clear Reset + 0 + + + ACMP0_SET + Set Reset + 0x1 + + + + + ADC0 + Analog-to-Digital converter reset control + 16 + 1 + read-write + + + ADC0_CLR + Clear Reset + 0 + + + ADC0_SET + Set Reset + 0x1 + + + + + SHSGPIO0 + Secure GPIO 0 reset control + 24 + 1 + read-write + + + SHSGPIO0_CLR + Clear Reset + 0 + + + SHSGPIO0_SET + Set Reset + 0x1 + + + + + + + PRSTCTL2 + Peripheral Reset Control Register 2 + 0x18 + 32 + read-write + 0x1C000001 + 0xFFFFFFFF + + + UTICK0 + Micro-tick timer reset control + 0 + 1 + read-write + + + UTICK0_CLR + Clear Reset + 0 + + + UTICK0_SET + Set Reset + 0x1 + + + + + WWDT0 + Watchdog timer reset control + 1 + 1 + read-write + + + WWDT0_CLR + Clear Reset + 0 + + + WWDT0_SET + Set Reset + 0x1 + + + + + + + PRSTCTL0_SET + Peripheral Reset Control Register 0 SET + 0x40 + 32 + write-only + 0 + 0 + + + DSP + Fusion_ DSP reset set + 1 + 1 + write-only + + + DSP_CLR + No Effect + 0 + + + DSP_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + AXI_SWITCH + AXI SWITCH reset set + 3 + 1 + write-only + + + AXI_SWITCH_CLR + No Effect + 0 + + + AXI_SWITCH_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + POWERQUAD + POWERQUAD reset set + 8 + 1 + write-only + + + POWERQUAD_CLR + No Effect + 0 + + + POWERQUAD_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + CASPER + CASPER reset set + 9 + 1 + write-only + + + CASPER_CLR + No Effect + 0 + + + CASPER_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + HASHCRYPT + HASHCRYPT reset set + 10 + 1 + write-only + + + HASHCRYPT_CLR + No Effect + 0 + + + HASHCRYPT_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + PUF + PUF reset set + 11 + 1 + write-only + + + PUF_CLR + No Effect + 0 + + + PUF_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + RNG + RNG reset set + 12 + 1 + write-only + + + RNG_CLR + No Effect + 0 + + + RNG_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + FLEXSPI0_OTFAD + FLEXSPI0 and OTFAD reset set + 16 + 1 + write-only + + + FLEXSPI0_OTFAD_CLR + No Effect + 0 + + + FLEXSPI0_OTFAD_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + FLEXSPI1 + FLEXSPI1 reset set + 18 + 1 + write-only + + + FLEXSPI1_CLR + No Effect + 0 + + + FLEXSPI1_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + USBHS_PHY + USB PHY reset set + 20 + 1 + write-only + + + USBHS_PHY_CLR + No Effect + 0 + + + USBHS_PHY_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + USBHS_DEVICE + USB Device reset set + 21 + 1 + write-only + + + USBHS_DEVICE_CLR + No Effect + 0 + + + USBHS_DEVICE_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + USBHS_HOST + USB HOST reset set + 22 + 1 + write-only + + + USBHS_HOST_CLR + No Effect + 0 + + + USBHS_HOST_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + USBHS_SRAM + USBHS SRAM reset set + 23 + 1 + write-only + + + USBHS_SRAM_CLR + No Effect + 0 + + + USBHS_SRAM_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + SCT + SCTimer reset set + 24 + 1 + write-only + + + SCT_CLR + No Effect + 0 + + + SCT_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + GPU + GPU reset set + 26 + 1 + write-only + + + GPU_CLR + No Effect + 0 + + + GPU_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + DISPLAY_CONTROLLER + LCDIF DISPLAY CONTROLLER reset set + 27 + 1 + write-only + + + DISPLAY_CONTROLLER_CLR + No Effect + 0 + + + DISPLAY_CONTROLLER_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + MIPI_DSI_CONTROLLER + MIPI DSI controller reset set + 28 + 1 + write-only + + + MIPI_DSI_CONTROLLER_CLR + No Effect + 0 + + + MIPI_DSI_CONTROLLER_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + MIPI_DSI_PHY + MIPI DSI PHY reset set + 29 + 1 + write-only + + + MIPI_DSI_PHY_CLR + No Effect + 0 + + + MIPI_DSI_PHY_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + SMARTDMA + SMARTDMA Event/Algorithm handler reset set + 30 + 1 + write-only + + + SMARTDMA_CLR + No Effect + 0 + + + SMARTDMA_SET + Sets the PRSTCTL0 Bit + 0x1 + + + + + + + PRSTCTL1_SET + Peripheral Reset Control Register 1 SET + 0x44 + 32 + write-only + 0 + 0 + + + SDIO0 + SDIO0 reset set + 2 + 1 + write-only + + + SDIO0_CLR + No effect + 0 + + + SDIO0_SET + Sets the PRSTCTL1 Bit + 0x1 + + + + + SDIO1 + SDIO1 reset set + 3 + 1 + write-only + + + SDIO1_CLR + No effect + 0 + + + SDIO1_SET + Sets the PRSTCTL1 Bit + 0x1 + + + + + ACMP0 + ACMP0 reset set + 15 + 1 + write-only + + + ACMP0_CLR + No effect + 0 + + + ACMP0_SET + Sets the PRSTCTL1 Bit + 0x1 + + + + + ADC0 + ADC0 reset set + 16 + 1 + write-only + + + ADC0_CLR + No effect + 0 + + + ADC0_SET + Sets the PRSTCTL1 Bit + 0x1 + + + + + SHSGPIO0 + SHSGPIO0 reset set + 24 + 1 + write-only + + + SHSGPIO0_CLR + No effect + 0 + + + SHSGPIO0_SET + Sets the PRSTCTL1 Bit + 0x1 + + + + + + + PRSTCTL2_SET + Peripheral Reset Control Register 2 SET + 0x48 + 32 + write-only + 0 + 0 + + + UTICK0 + Micro-tick timer 0 reset set + 0 + 1 + write-only + + + UTICK0_CLR + No effect + 0 + + + UTICK0_SET + Sets the PRSTCTL2 Bit + 0x1 + + + + + WWDT0 + WWDT0 reset set + 1 + 1 + write-only + + + WWDT0_CLR + No effect + 0 + + + WWDT0_SET + Sets the PRSTCTL2 Bit + 0x1 + + + + + + + PRSTCTL0_CLR + Peripheral Reset Control Register 0 CLR + 0x70 + 32 + write-only + 0 + 0 + + + DSP + Fusion_ F1 DSP reset clear + 1 + 1 + write-only + + + DSP_CLR + No effect + 0 + + + DSP_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + AXI_SWITCH + AXI SWITCH reset clear + 3 + 1 + write-only + + + AXI_SWITCH_CLR + No effect + 0 + + + AXI_SWITCH_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + POWERQUAD + POWERQUAD reset clear + 8 + 1 + write-only + + + POWERQUAD_CLR + No effect + 0 + + + POWERQUAD_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + CASPER + CASPER reset clear + 9 + 1 + write-only + + + CASPER_CLR + No effect + 0 + + + CASPER_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + HASHCRYPT + HASHCRYPT reset clear + 10 + 1 + write-only + + + HASHCRYPT_CLR + No effect + 0 + + + HASHCRYPT_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + PUF + PUF reset clear + 11 + 1 + write-only + + + PUF_CLR + No effect + 0 + + + PUF_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + RNG + RNG reset clear + 12 + 1 + write-only + + + RNG_CLR + No effect + 0 + + + RNG_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + FLEXSPI0_OTFAD + FLEXSPI0 and OTFAD reset clear + 16 + 1 + write-only + + + FLEXSPI0_OTFAD_CLR + No effect + 0 + + + FLEXSPI0_OTFAD_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + FLEXSPI1 + FLEXSPI1 reset clear + 18 + 1 + write-only + + + FLEXSPI1_CLR + No effect + 0 + + + FLEXSPI1_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + USBHS_PHY + USB PHY reset clear + 20 + 1 + write-only + + + USBHS_PHY_CLR + No effect + 0 + + + USBHS_PHY_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + USBHS_DEVICE + USB DEVICE reset clear + 21 + 1 + write-only + + + USBHS_DEVICE_CLR + No effect + 0 + + + USBHS_DEVICE_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + USBHS_HOST + USB HOST reset clear + 22 + 1 + write-only + + + USBHS_HOST_CLR + No effect + 0 + + + USBHS_HOST_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + USBHS_SRAM + USBHS SRAM reset clear + 23 + 1 + write-only + + + USBHS_SRAM_CLR + No effect + 0 + + + USBHS_SRAM_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + SCT + SCT reset clear + 24 + 1 + write-only + + + SCT_CLR + No effect + 0 + + + SCT_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + GPU + GPU reset clear + 26 + 1 + write-only + + + GPU_CLR + No effect + 0 + + + GPU_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + DISPLAY_CONTROLLER + LCDIF DISPLAY CONTROLLER reset clear + 27 + 1 + write-only + + + DISPLAY_CONTROLLER_CLR + No effect + 0 + + + DISPLAY_CONTROLLER_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + MIPI_DSI_CONTROLLER + MIPI DSI controller reset clear + 28 + 1 + write-only + + + MIPI_DSI_CONTROLLER_CLR + No effect + 0 + + + MIPI_DSI_CONTROLLER_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + MIPI_DSI_PHY + MIPI DSI PHY reset clear + 29 + 1 + write-only + + + MIPI_DSI_PHY_CLR + No effect + 0 + + + MIPI_DSI_PHY_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + SMARTDMA + SMARTDMA Event/Algorithm handler reset clear + 30 + 1 + write-only + + + SMARTDMA_CLR + No effect + 0 + + + SMARTDMA_SET + Clears the PRSTCTL0 Bit + 0x1 + + + + + + + PRSTCTL1_CLR + Peripheral Reset Control Register 1 CLR + 0x74 + 32 + write-only + 0 + 0 + + + SDIO0 + SDIO0 reset clear + 2 + 1 + write-only + + + SDIO0_CLR + No effect + 0 + + + SDIO0_SET + Clears the PRSTCTL1 Bit + 0x1 + + + + + SDIO1 + SDIO1 reset clear + 3 + 1 + write-only + + + SDIO1_CLR + No effect + 0 + + + SDIO1_SET + Clears the PRSTCTL1 Bit + 0x1 + + + + + ACMP0 + ACMP0 reset clear + 15 + 1 + write-only + + + ACMP0_CLR + No effect + 0 + + + ACMP0_SET + Clears the PRSTCTL1 Bit + 0x1 + + + + + ADC0 + ADC0 reset clear + 16 + 1 + write-only + + + ADC0_CLR + No effect + 0 + + + ADC0_SET + Clears the PRSTCTL1 Bit + 0x1 + + + + + SHSGPIO0 + Secure HSGPIO0 reset clear + 24 + 1 + write-only + + + SHSGPIO0_CLR + No effect + 0 + + + SHSGPIO0_SET + Clears the PRSTCTL1 Bit + 0x1 + + + + + + + PRSTCTL2_CLR + Peripheral Reset Control Register 2 CLR + 0x78 + 32 + write-only + 0 + 0 + + + UTICK0 + Micro-tick timer 0 reset clear + 0 + 1 + write-only + + + UTICK0_CLR + No effect + 0 + + + UTICK0_SET + Clears the PRSTCTL2 Bit + 0x1 + + + + + WWDT0 + WWDT0 reset clear + 1 + 1 + write-only + + + WWDT0_CLR + No effect + 0 + + + WWDT0_SET + Clears the PRSTCTL2 Bit + 0x1 + + + + + + + + + \ No newline at end of file -- 2.46.0.rc2.264.g509ed76dc8-goog