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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240625104039.48311-1-linux.amoon@gmail.com> On Tue, Jun 25, 2024 at 04:10:32PM +0530, Anand Moon wrote: > Refactor the clock handling in the Rockchip PCIe driver, > introducing a more robust and efficient method for enabling and > disabling clocks using clk_bulk*() API. Using the clk_bulk APIs, > the clock handling for the core clocks becomes much simpler. > Why can't you just use devm_clk_bulk_get_all()? This gets rid of hardcoding the clock names in driver. - Mani > Signed-off-by: Anand Moon > --- > v4: use dev_err_probe for error patch. > v3: Fix typo in commit message, dropped reported by. > v2: Fix compilation error reported by Intel test robot. > --- > drivers/pci/controller/pcie-rockchip.c | 68 ++++---------------------- > drivers/pci/controller/pcie-rockchip.h | 15 ++++-- > 2 files changed, 21 insertions(+), 62 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > index 0ef2e622d36e..804135511528 100644 > --- a/drivers/pci/controller/pcie-rockchip.c > +++ b/drivers/pci/controller/pcie-rockchip.c > @@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > struct platform_device *pdev = to_platform_device(dev); > struct device_node *node = dev->of_node; > struct resource *regs; > - int err; > + int err, i; > > if (rockchip->is_rc) { > regs = platform_get_resource_byname(pdev, > @@ -127,29 +127,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > "failed to get ep GPIO\n"); > } > > - rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); > - if (IS_ERR(rockchip->aclk_pcie)) { > - dev_err(dev, "aclk clock not found\n"); > - return PTR_ERR(rockchip->aclk_pcie); > - } > - > - rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf"); > - if (IS_ERR(rockchip->aclk_perf_pcie)) { > - dev_err(dev, "aclk_perf clock not found\n"); > - return PTR_ERR(rockchip->aclk_perf_pcie); > - } > - > - rockchip->hclk_pcie = devm_clk_get(dev, "hclk"); > - if (IS_ERR(rockchip->hclk_pcie)) { > - dev_err(dev, "hclk clock not found\n"); > - return PTR_ERR(rockchip->hclk_pcie); > - } > + for (i = 0; i < ROCKCHIP_NUM_CLKS; i++) > + rockchip->clks[i].id = rockchip_pci_clks[i]; > > - rockchip->clk_pcie_pm = devm_clk_get(dev, "pm"); > - if (IS_ERR(rockchip->clk_pcie_pm)) { > - dev_err(dev, "pm clock not found\n"); > - return PTR_ERR(rockchip->clk_pcie_pm); > - } > + err = devm_clk_bulk_get(dev, ROCKCHIP_NUM_CLKS, rockchip->clks); > + if (err) > + return dev_err_probe(dev, err, "failed to get clocks\n"); > > return 0; > } > @@ -372,39 +355,11 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) > struct device *dev = rockchip->dev; > int err; > > - err = clk_prepare_enable(rockchip->aclk_pcie); > - if (err) { > - dev_err(dev, "unable to enable aclk_pcie clock\n"); > - return err; > - } > - > - err = clk_prepare_enable(rockchip->aclk_perf_pcie); > - if (err) { > - dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); > - goto err_aclk_perf_pcie; > - } > - > - err = clk_prepare_enable(rockchip->hclk_pcie); > - if (err) { > - dev_err(dev, "unable to enable hclk_pcie clock\n"); > - goto err_hclk_pcie; > - } > - > - err = clk_prepare_enable(rockchip->clk_pcie_pm); > - if (err) { > - dev_err(dev, "unable to enable clk_pcie_pm clock\n"); > - goto err_clk_pcie_pm; > - } > + err = clk_bulk_prepare_enable(ROCKCHIP_NUM_CLKS, rockchip->clks); > + if (err) > + return dev_err_probe(dev, err, "failed to enable clocks\n"); > > return 0; > - > -err_clk_pcie_pm: > - clk_disable_unprepare(rockchip->hclk_pcie); > -err_hclk_pcie: > - clk_disable_unprepare(rockchip->aclk_perf_pcie); > -err_aclk_perf_pcie: > - clk_disable_unprepare(rockchip->aclk_pcie); > - return err; > } > EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); > > @@ -412,10 +367,7 @@ void rockchip_pcie_disable_clocks(void *data) > { > struct rockchip_pcie *rockchip = data; > > - clk_disable_unprepare(rockchip->clk_pcie_pm); > - clk_disable_unprepare(rockchip->hclk_pcie); > - clk_disable_unprepare(rockchip->aclk_perf_pcie); > - clk_disable_unprepare(rockchip->aclk_pcie); > + clk_bulk_disable_unprepare(ROCKCHIP_NUM_CLKS, rockchip->clks); > } > EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); > > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h > index 6111de35f84c..72346e17e45e 100644 > --- a/drivers/pci/controller/pcie-rockchip.h > +++ b/drivers/pci/controller/pcie-rockchip.h > @@ -11,6 +11,7 @@ > #ifndef _PCIE_ROCKCHIP_H > #define _PCIE_ROCKCHIP_H > > +#include > #include > #include > #include > @@ -287,6 +288,15 @@ > (((c) << ((b) * 8 + 5)) & \ > ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) > > +#define ROCKCHIP_NUM_CLKS ARRAY_SIZE(rockchip_pci_clks) > + > +static const char * const rockchip_pci_clks[] = { > + "aclk", > + "aclk-perf", > + "hclk", > + "pm", > +}; > + > struct rockchip_pcie { > void __iomem *reg_base; /* DT axi-base */ > void __iomem *apb_base; /* DT apb-base */ > @@ -299,10 +309,7 @@ struct rockchip_pcie { > struct reset_control *pm_rst; > struct reset_control *aclk_rst; > struct reset_control *pclk_rst; > - struct clk *aclk_pcie; > - struct clk *aclk_perf_pcie; > - struct clk *hclk_pcie; > - struct clk *clk_pcie_pm; > + struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; > struct regulator *vpcie12v; /* 12V power supply */ > struct regulator *vpcie3v3; /* 3.3V power supply */ > struct regulator *vpcie1v8; /* 1.8V power supply */ > > base-commit: 35bb670d65fc0f80c62383ab4f2544cec85ac57a > -- > 2.44.0 > > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2FA5EC3DA7F for ; Thu, 15 Aug 2024 16:12:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: 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d9443c01a7336-201f1c88834sm10573375ad.255.2024.08.15.09.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 09:11:43 -0700 (PDT) Date: Thu, 15 Aug 2024 21:41:35 +0530 From: Manivannan Sadhasivam To: Anand Moon Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function Message-ID: <20240815161135.GE2562@thinkpad> References: <20240625104039.48311-1-linux.amoon@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240625104039.48311-1-linux.amoon@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240815_171147_698536_7A301DA7 X-CRM114-Status: GOOD ( 26.03 ) X-BeenThere: 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