Re: [PATCH 16/16] iommupt: Add the Intel VT-D second stage page table format

[Jason Gunthorpe <jgg@nvidia.com>]

On Mon, Aug 19, 2024 at 02:51:11AM +0000, Zhang, Tina wrote:

> > +/* Shared descriptor bits */
> > +enum {
> > +	VTDSS_FMT_R = BIT(0),
> > +	VTDSS_FMT_W = BIT(1),
> > +	VTDSS_FMT_X = BIT(2),
> 
> VT-d Spec doesn't have this BIT(2) defined.

It does:

 Figure 9-8. Format for Second-Stage Paging Entries

 Bit 2 = X^1

 1. X field is ignored by hardware if Execute Request Support (ERS) is
 reported as Clear in the Extended Capability Register or if SSEE=0 in
 the scalable-mode PASID-table entry referencing the second-stage
 paging entries.

> > +static struct io_pgtable_ops *
> > +vtdss_pt_iommu_alloc_io_pgtable(struct pt_iommu_vtdss_cfg *cfg,
> > +				struct device *iommu_dev,
> > +				struct io_pgtable_cfg **unused_pgtbl_cfg) {
> > +	struct io_pgtable_cfg pgtbl_cfg = {};
> > +
> > +	pgtbl_cfg.ias = 48;
> > +	pgtbl_cfg.oas = 52;
> 
> Since the alloca_io_pgtable_ops() is used for PT allocation, the
> pgtbl_cfg.ias and pgtbl_cfg.oas can be provided with the theoretical
> max address sizes or simply leave them unassigned here.

It doesn't work if they are unassigned. The map op returns EFAULT.

Thanks,
Jason