Re: [PATCH v4 14/18] KVM: arm64: nv: Add SW walker for AT S1 emulation

[kernel test robot <lkp@intel.com>]

Hi Marc,

kernel test robot noticed the following build warnings:

[auto build test WARNING on kvmarm/next]
[also build test WARNING on arm64/for-next/core soc/for-next linus/master v6.11-rc4 next-20240821]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Marc-Zyngier/arm64-Add-missing-APTable-and-TCR_ELx-HPD-masks/20240820-184117
base:   https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git next
patch link:    https://lore.kernel.org/r/20240820103756.3545976-15-maz%40kernel.org
patch subject: [PATCH v4 14/18] KVM: arm64: nv: Add SW walker for AT S1 emulation
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20240822/202408220101.bqH2w4z5-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240822/202408220101.bqH2w4z5-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408220101.bqH2w4z5-lkp@intel.com/

All warnings (new ones prefixed by >>):

   arch/arm64/kvm/at.c: In function 'handle_at_slow':
>> arch/arm64/kvm/at.c:736:45: warning: variable 'px' set but not used [-Wunused-but-set-variable]
     736 |         bool perm_fail, ur, uw, ux, pr, pw, px;
         |                                             ^~
   arch/arm64/kvm/at.c: In function '__kvm_at_s1e2':
   arch/arm64/kvm/at.c:973:36: warning: variable 'mmu' set but not used [-Wunused-but-set-variable]
     973 |                 struct kvm_s2_mmu *mmu;
         |                                    ^~~


vim +/px +736 arch/arm64/kvm/at.c

   733	
   734	static u64 handle_at_slow(struct kvm_vcpu *vcpu, u32 op, u64 vaddr)
   735	{
 > 736		bool perm_fail, ur, uw, ux, pr, pw, px;
   737		struct s1_walk_result wr = {};
   738		struct s1_walk_info wi = {};
   739		int ret, idx;
   740	
   741		ret = setup_s1_walk(vcpu, op, &wi, &wr, vaddr);
   742		if (ret)
   743			goto compute_par;
   744	
   745		if (wr.level == S1_MMU_DISABLED)
   746			goto compute_par;
   747	
   748		idx = srcu_read_lock(&vcpu->kvm->srcu);
   749	
   750		ret = walk_s1(vcpu, &wi, &wr, vaddr);
   751	
   752		srcu_read_unlock(&vcpu->kvm->srcu, idx);
   753	
   754		if (ret)
   755			goto compute_par;
   756	
   757		/* FIXME: revisit when adding indirect permission support */
   758		/* AArch64.S1DirectBasePermissions() */
   759		if (wi.regime != TR_EL2) {
   760			switch (FIELD_GET(PTE_USER | PTE_RDONLY, wr.desc)) {
   761			case 0b00:
   762				pr = pw = true;
   763				ur = uw = false;
   764				break;
   765			case 0b01:
   766				pr = pw = ur = uw = true;
   767				break;
   768			case 0b10:
   769				pr = true;
   770				pw = ur = uw = false;
   771				break;
   772			case 0b11:
   773				pr = ur = true;
   774				pw = uw = false;
   775				break;
   776			}
   777	
   778			switch (wr.APTable) {
   779			case 0b00:
   780				break;
   781			case 0b01:
   782				ur = uw = false;
   783				break;
   784			case 0b10:
   785				pw = uw = false;
   786				break;
   787			case 0b11:
   788				pw = ur = uw = false;
   789				break;
   790			}
   791	
   792			/* We don't use px for anything yet, but hey... */
   793			px = !((wr.desc & PTE_PXN) || wr.PXNTable || uw);
   794			ux = !((wr.desc & PTE_UXN) || wr.UXNTable);
   795	
   796			if (op == OP_AT_S1E1RP || op == OP_AT_S1E1WP) {
   797				bool pan;
   798	
   799				pan = *vcpu_cpsr(vcpu) & PSR_PAN_BIT;
   800				pan &= ur || uw;
   801				pw &= !pan;
   802				pr &= !pan;
   803			}
   804		} else {
   805			ur = uw = ux = false;
   806	
   807			if (!(wr.desc & PTE_RDONLY)) {
   808				pr = pw = true;
   809			} else {
   810				pr = true;
   811				pw = false;
   812			}
   813	
   814			if (wr.APTable & BIT(1))
   815				pw = false;
   816	
   817			/* XN maps to UXN */
   818			px = !((wr.desc & PTE_UXN) || wr.UXNTable);
   819		}
   820	
   821		perm_fail = false;
   822	
   823		switch (op) {
   824		case OP_AT_S1E1RP:
   825		case OP_AT_S1E1R:
   826		case OP_AT_S1E2R:
   827			perm_fail = !pr;
   828			break;
   829		case OP_AT_S1E1WP:
   830		case OP_AT_S1E1W:
   831		case OP_AT_S1E2W:
   832			perm_fail = !pw;
   833			break;
   834		case OP_AT_S1E0R:
   835			perm_fail = !ur;
   836			break;
   837		case OP_AT_S1E0W:
   838			perm_fail = !uw;
   839			break;
   840		default:
   841			BUG();
   842		}
   843	
   844		if (perm_fail)
   845			fail_s1_walk(&wr, ESR_ELx_FSC_PERM_L(wr.level), false, false);
   846	
   847	compute_par:
   848		return compute_par_s1(vcpu, &wr, wi.regime);
   849	}
   850	

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