From mboxrd@z Thu Jan 1 00:00:00 1970 From: Xianwei Zhao Date: Fri, 23 Aug 2024 17:19:45 +0800 Subject: [PATCH 2/3] rtc: support for the Amlogic on-chip RTC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20240823-rtc-v1-2-6f70381da283@amlogic.com> References: <20240823-rtc-v1-0-6f70381da283@amlogic.com> In-Reply-To: <20240823-rtc-v1-0-6f70381da283@amlogic.com> To: Yiting Deng , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724404784; l=18890; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=uTuv7es8G0Sz0X0k67EdKdNym5NaaQd1YXkQ9wf35M4=; b=ZUApP7jYDGTGxZXNq3YBnYVcupXPyw+l7ig8jWctgOzmcEMQhKeVw3E/OjXJet7lZoRLyVJpm qozz4edsE9+DWo3n2AnMzK0F7Ze7cxR4oX2cQOMJeykgwdT5KrQY81e X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 List-Id: B4 Relay Submissions From: Yiting Deng Support for the on-chip RTC found in some of Amlogic's SoCs such as the A113L2 and A113X2. Signed-off-by: Yiting Deng Signed-off-by: Xianwei Zhao --- drivers/rtc/Kconfig | 12 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-amlogic.c | 589 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 602 insertions(+) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2a95b05982ad..0dd042701c3b 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -2043,4 +2043,16 @@ config RTC_DRV_SSD202D This driver can also be built as a module, if so, the module will be called "rtc-ssd20xd". +config RTC_DRV_AMLOGIC + tristate "Amlogic RTC" + depends on ARCH_MESON || COMPILE_TEST + select REGMAP_MMIO + default y + help + If you say yes here you get support for the RTC block on the + Amlogic A113L2(A4) and A113X2(A5) SoCs. + + This driver can also be built as a module. If so, the module + will be called "rtc-amlogic". + endif # RTC_CLASS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 3004e372f25f..d4a56ddb4246 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_RTC_DRV_ABB5ZES3) += rtc-ab-b5ze-s3.o obj-$(CONFIG_RTC_DRV_ABEOZ9) += rtc-ab-eoz9.o obj-$(CONFIG_RTC_DRV_ABX80X) += rtc-abx80x.o obj-$(CONFIG_RTC_DRV_AC100) += rtc-ac100.o +obj-$(CONFIG_RTC_DRV_AMLOGIC) += rtc-amlogic.o obj-$(CONFIG_RTC_DRV_ARMADA38X) += rtc-armada38x.o obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o obj-$(CONFIG_RTC_DRV_ASM9260) += rtc-asm9260.o diff --git a/drivers/rtc/rtc-amlogic.c b/drivers/rtc/rtc-amlogic.c new file mode 100644 index 000000000000..7c681a2320d3 --- /dev/null +++ b/drivers/rtc/rtc-amlogic.c @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2024 Amlogic, Inc. All rights reserved + * Author: Yiting Deng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* rtc oscillator rate */ +#define OSC_32K (32768) +#define OSC_24M (24000000) + +#define RTC_CTRL (0x0 << 2) /* Control RTC */ +#define RTC_ALRM0_EN BIT(0) +#define RTC_OSC_SEL BIT(8) +#define RTC_ENABLE BIT(12) + +#define RTC_COUNTER_REG (0x1 << 2) /* Program RTC counter initial value */ + +#define RTC_ALARM0_REG (0x2 << 2) /* Program RTC alarm0 value */ + +#define RTC_SEC_ADJUST_REG (0x6 << 2) /* Control second-based timing adjustment */ +#define RTC_MATCH_COUNTER GENMASK(18, 0) +#define RTC_SEC_ADJUST_CTRL GENMASK(20, 19) +#define RTC_ADJ_VALID BIT(23) +#define RTC_DIV256_ADJ_VAL BIT(24) +#define RTC_DIV256_ADJ_DSR BIT(25) + +#define RTC_INT_MASK (0x8 << 2) /* RTC interrupt mask */ +#define RTC_ALRM0_IRQ_MSK BIT(0) + +#define RTC_INT_CLR (0x9 << 2) /* Clear RTC interrupt */ +#define RTC_ALRM0_IRQ_CLR BIT(0) + +#define RTC_OSCIN_CTRL0 (0xa << 2) /* Control RTC clk from 24M */ +#define RTC_OSCIN_CTRL1 (0xb << 2) /* Control RTC clk from 24M */ +#define RTC_OSCIN_IN_EN BIT(31) +#define RTC_OSCIN_OUT_CFG GENMASK(29, 28) +#define RTC_OSCIN_OUT_N0M0 GENMASK(11, 0) +#define RTC_OSCIN_OUT_N1M1 GENMASK(23, 12) + +#define RTC_INT_STATUS (0xc << 2) /* RTC interrupt status */ +#define RTC_ALRM0_IRQ_STATUS BIT(0) + +#define RTC_REAL_TIME (0xd << 2) /* RTC time value */ + +#define RTC_OSCIN_OUT_32K_N0 0x2dc +#define RTC_OSCIN_OUT_32K_N1 0x2db +#define RTC_OSCIN_OUT_32K_M0 0x1 +#define RTC_OSCIN_OUT_32K_M1 0x2 + +struct aml_rtc_config { + bool gray_stored; +}; + +struct aml_rtc_data { + struct regmap *map; + struct rtc_device *rtc_dev; + int irq; + struct clk *sclk; + const struct aml_rtc_config *config; +}; + +static const struct regmap_config aml_rtc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = RTC_REAL_TIME, +}; + +static u32 gray_to_binary(u32 gray) +{ + u32 bcd = gray; + int size = sizeof(bcd) * 8; + int i; + + for (i = 0; (1 << i) < size; i++) + bcd ^= bcd >> (1 << i); + + return bcd; +} + +static u32 binary_to_gray(u32 bcd) +{ + return bcd ^ (bcd >> 1); +} + +static void aml_set_time(struct aml_rtc_data *rtc, u32 time_sec) +{ + if (rtc->config->gray_stored) + time_sec = binary_to_gray(time_sec); + regmap_write(rtc->map, RTC_COUNTER_REG, time_sec); +} + +static u32 aml_read_time(struct aml_rtc_data *rtc) +{ + u32 time_sec; + + regmap_read(rtc->map, RTC_REAL_TIME, &time_sec); + if (rtc->config->gray_stored) + time_sec = gray_to_binary(time_sec); + return time_sec; +} + +static u32 aml_read_alarm(struct aml_rtc_data *rtc) +{ + u32 alarm_sec; + + regmap_read(rtc->map, RTC_ALARM0_REG, &alarm_sec); + if (rtc->config->gray_stored) + alarm_sec = gray_to_binary(alarm_sec); + return alarm_sec; +} + +static void aml_set_alarm(struct aml_rtc_data *rtc, u32 alarm_sec) +{ + if (rtc->config->gray_stored) + alarm_sec = binary_to_gray(alarm_sec); + regmap_write(rtc->map, RTC_ALARM0_REG, alarm_sec); +} + +static int aml_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + u32 time_sec; + + time_sec = aml_read_time(rtc); + rtc_time64_to_tm(time_sec, tm); + dev_dbg(dev, "%s: read time = %us\n", __func__, time_sec); + + return 0; +} + +static int aml_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + u32 time_sec; + + time_sec = rtc_tm_to_time64(tm); + aml_set_time(rtc, time_sec); + dev_dbg(dev, "%s: set time = %us\n", __func__, time_sec); + + return 0; +} + +static int aml_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + time64_t alarm_sec; + + if (alarm->enabled) { + regmap_update_bits(rtc->map, RTC_CTRL, + RTC_ALRM0_EN, RTC_ALRM0_EN); + regmap_update_bits(rtc->map, RTC_INT_MASK, + RTC_ALRM0_IRQ_MSK, 0); + + alarm_sec = rtc_tm_to_time64(&alarm->time); + if (alarm_sec > U32_MAX) { + dev_err(dev, "alarm value invalid!\n"); + return -EINVAL; + } + aml_set_alarm(rtc, alarm_sec); + } + dev_dbg(dev, "%s: alarm->enabled=%d alarm_set=%llds\n", __func__, + alarm->enabled, alarm_sec); + + return 0; +} + +static int aml_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + u32 alarm_sec; + u32 reg_val; + int alarm_enable, alarm_mask; + + alarm_sec = aml_read_alarm(rtc); + rtc_time64_to_tm(alarm_sec, &alarm->time); + + regmap_read(rtc->map, RTC_CTRL, ®_val); + alarm_enable = FIELD_GET(RTC_ALRM0_EN, reg_val); + + regmap_read(rtc->map, RTC_INT_MASK, ®_val); + alarm_mask = FIELD_GET(RTC_ALRM0_IRQ_MSK, reg_val); + + alarm->enabled = (alarm_enable && !alarm_mask) ? 1 : 0; + dev_dbg(dev, "%s: alarm->enabled=%d alarm=%us\n", __func__, + alarm->enabled, alarm_sec); + + return 0; +} + +static int aml_rtc_alarm_enable(struct device *dev, unsigned int enabled) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + + if (enabled) { + regmap_update_bits(rtc->map, RTC_CTRL, + RTC_ALRM0_EN, RTC_ALRM0_EN); + regmap_update_bits(rtc->map, RTC_INT_MASK, + RTC_ALRM0_IRQ_MSK, 0); + } else { + regmap_update_bits(rtc->map, RTC_INT_MASK, + RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK); + regmap_update_bits(rtc->map, RTC_CTRL, + RTC_ALRM0_EN, 0); + } + + return 0; +} + +static const struct rtc_class_ops aml_rtc_ops = { + .read_time = aml_rtc_read_time, + .set_time = aml_rtc_set_time, + .read_alarm = aml_rtc_read_alarm, + .set_alarm = aml_rtc_set_alarm, + .alarm_irq_enable = aml_rtc_alarm_enable, +}; + +static irqreturn_t aml_rtc_handler(int irq, void *data) +{ + struct aml_rtc_data *rtc = (struct aml_rtc_data *)data; + + regmap_write(rtc->map, RTC_ALARM0_REG, 0); + regmap_update_bits(rtc->map, RTC_INT_CLR, + RTC_ALRM0_IRQ_STATUS, RTC_ALRM0_IRQ_STATUS); + + rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return IRQ_HANDLED; +} + +static int aml_rtc_adjust_sec(struct device *dev, u32 match_counter, + int ops, int enable) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev->parent); + u32 reg_val; + + if (!FIELD_FIT(RTC_MATCH_COUNTER, match_counter)) { + pr_err("%s: invalid match_counter\n", __func__); + return -EINVAL; + } + + reg_val = FIELD_PREP(RTC_SEC_ADJUST_CTRL, ops) + | FIELD_PREP(RTC_MATCH_COUNTER, match_counter) + | FIELD_PREP(RTC_ADJ_VALID, enable); + /* Set sec_adjust_ctrl, match_counter and Valid adjust */ + regmap_write(rtc->map, RTC_SEC_ADJUST_REG, reg_val); + + return 0; +} + +static int aml_rtc_set_calibration(struct device *dev, u32 calibration) +{ + int cal_ops, enable, match_counter; + int ret; + + match_counter = FIELD_GET(RTC_MATCH_COUNTER, calibration); + cal_ops = FIELD_GET(RTC_SEC_ADJUST_CTRL, calibration); + enable = FIELD_GET(RTC_ADJ_VALID, calibration); + + ret = aml_rtc_adjust_sec(dev, match_counter, cal_ops, enable); + dev_dbg(dev, "%s: Success to store RTC calibration attribute\n", + __func__); + + return ret; +} + +static int aml_rtc_get_calibration(struct device *dev, u32 *calibration) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev->parent); + u32 reg_val; + + regmap_read(rtc->map, RTC_SEC_ADJUST_REG, ®_val); + *calibration = FIELD_GET(RTC_SEC_ADJUST_CTRL | RTC_MATCH_COUNTER, reg_val); + /* BIT is only UL defined，and GENMASK has no type, its' donot used together */ + *calibration |= FIELD_PREP(RTC_ADJ_VALID, FIELD_GET(RTC_ADJ_VALID, reg_val)); + + return 0; +} + +/** + * The calibration value transferred from buf takes bit[18:0] to represent + * match_counter, while takes bit[20:19] to represent sec_adjust_ctrl, bit[23] + * to represent adj_valid. enable/disable sec_adjust_ctrl and match_counter. + * @buf: Separate buf to match_counter, sec_adjust_ctrl and adj_valid + * match_counter: bit[18:0], value is 0 ~ 0x7fff + * sec_adjust_ctrl: bit[20:19], value is 0 ~ 2. 3 to insert a second once every + * match_counter+1 seconds, 2 to swallow a second once every match_counter+1 seconds + * 0 or 1 to no adjustment + * adj_valid: bit[23], value is 0 or 1, 0 to disable sec_adjust_ctrl and + * match_counter, and 1 to enable them. + */ +static ssize_t rtc_calibration_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int retval; + int calibration = 0; + + if (sscanf(buf, " %i ", &calibration) != 1) { + dev_err(dev, "Failed to store RTC calibration attribute\n"); + return -EINVAL; + } + retval = aml_rtc_set_calibration(dev, calibration); + + return retval ? retval : count; +} + +static ssize_t rtc_calibration_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval = 0; + u32 calibration = 0; + + retval = aml_rtc_get_calibration(dev, &calibration); + if (retval < 0) { + dev_err(dev, "Failed to read RTC calibration attribute\n"); + sprintf(buf, "0\n"); + return retval; + } + + return sprintf(buf, "0x%x\n", calibration); +} +static DEVICE_ATTR_RW(rtc_calibration); + +static int rtc_set_div256_adjust(struct device *dev, u32 *value) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev->parent); + u32 div256_adj; + + div256_adj = FIELD_PREP(RTC_DIV256_ADJ_DSR | RTC_DIV256_ADJ_VAL, *value); + /* + * AO_RTC_SEC_ADJUST_REG bit 24 insert/remove(1/0) a div256 cycle, + * bit 25 valid/invalid(1/0) div256_adj_val + */ + regmap_write_bits(rtc->map, RTC_SEC_ADJUST_REG, + RTC_DIV256_ADJ_DSR | RTC_DIV256_ADJ_VAL, div256_adj); + /* rtc need about 30ms to adjust its time after written */ + mdelay(30); + + return 0; +} + +static int rtc_get_div256_adjust(struct device *dev, u32 *value) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev->parent); + u32 reg_val; + + regmap_read(rtc->map, RTC_SEC_ADJUST_REG, ®_val); + *value = FIELD_GET(RTC_DIV256_ADJ_DSR | RTC_DIV256_ADJ_VAL, reg_val); + + return 0; +} + +/** + * div256 adjust function is controlled using bit[24] and bit[25]. + * transferred buf takes bit[0] to represent div256 adj val, bit[1] + * to represent div256 adj enable/disable. div256 cycle means that adjust + * 1/32768/256 once by written once, it's val is equal to 1/128s + * @buf: 3: enable div256 adjust and insert a div256 cycle + * 2: enable div256 adjust and remove a div256 cycle + * 1 or 0: disable div256 adjust + */ +static ssize_t rtc_div256_adjust_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int retval; + u32 value = 0; + + if (sscanf(buf, " %i ", &value) != 1) { + dev_err(dev, "Failed to store RTC div256 adjust attribute\n"); + return -EINVAL; + } + retval = rtc_set_div256_adjust(dev, &value); + + return retval ? retval : count; +} + +static ssize_t rtc_div256_adjust_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval = 0; + u32 value = 0; + + retval = rtc_get_div256_adjust(dev, &value); + if (retval < 0) { + dev_err(dev, "Failed to read RTC div256 adjust attribute\n"); + sprintf(buf, "0\n"); + return retval; + } + + return sprintf(buf, "0x%x\n", value); +} +static DEVICE_ATTR_RW(rtc_div256_adjust); + +static struct attribute *aml_rtc_attrs[] = { + &dev_attr_rtc_calibration.attr, + &dev_attr_rtc_div256_adjust.attr, + NULL, +}; + +static const struct attribute_group aml_rtc_sysfs_files = { + .attrs = aml_rtc_attrs, +}; + +static void aml_rtc_init(struct device *dev, struct aml_rtc_data *rtc) +{ + u32 reg_val; + u32 rtc_enable; + + regmap_read(rtc->map, RTC_CTRL, ®_val); + rtc_enable = FIELD_GET(RTC_ENABLE, reg_val); + if (!rtc_enable) { + if (clk_get_rate(rtc->sclk) == OSC_24M) { + /* select 24M oscillator */ + regmap_update_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, RTC_OSC_SEL); + + /* + * Set RTC oscillator to freq_out to freq_in/((N0*M0+N1*M1)/(M0+M1)) + * Enable clock_in gate of oscillator 24MHz + * Set N0 to 733, N1 to 732 + */ + reg_val = FIELD_PREP(RTC_OSCIN_IN_EN, 1) + | FIELD_PREP(RTC_OSCIN_OUT_CFG, 1) + | FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_N0) + | FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_N1); + regmap_write_bits(rtc->map, RTC_OSCIN_CTRL0, RTC_OSCIN_IN_EN + | RTC_OSCIN_OUT_CFG | RTC_OSCIN_OUT_N0M0 + | RTC_OSCIN_OUT_N1M1, reg_val); + + /* Set M0 to 2, M1 to 3, so freq_out = 32768 Hz*/ + reg_val = FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_M0) + | FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_M1); + regmap_write_bits(rtc->map, RTC_OSCIN_CTRL1, RTC_OSCIN_OUT_N0M0 + | RTC_OSCIN_OUT_N1M1, reg_val); + } else { + /* select 32K oscillator */ + regmap_write_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, 0); + } + /* Enable RTC */ + regmap_write_bits(rtc->map, RTC_CTRL, RTC_ENABLE, RTC_ENABLE); + usleep_range(100, 200); + } + regmap_write_bits(rtc->map, RTC_INT_MASK, + RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK); + regmap_write_bits(rtc->map, RTC_CTRL, RTC_ALRM0_EN, 0); +} + +static int aml_rtc_probe(struct platform_device *pdev) +{ + struct aml_rtc_data *rtc; + void __iomem *base; + struct clk *core_clk; + int ret = 0; + + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + + rtc->config = of_device_get_match_data(&pdev->dev); + if (!rtc->config) + return -ENODEV; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(&pdev->dev, "resource ioremap failed\n"); + return PTR_ERR(base); + } + + rtc->map = devm_regmap_init_mmio(&pdev->dev, base, &aml_rtc_regmap_config); + if (IS_ERR(rtc->map)) { + dev_err(&pdev->dev, "regmap init failed\n"); + return PTR_ERR(rtc->map); + } + + rtc->irq = platform_get_irq(pdev, 0); + if (rtc->irq < 0) + return rtc->irq; + + rtc->sclk = devm_clk_get(&pdev->dev, "rtc_osc"); + if (IS_ERR(rtc->sclk)) + return PTR_ERR(rtc->sclk); + if (clk_get_rate(rtc->sclk) != OSC_32K && clk_get_rate(rtc->sclk) != OSC_24M) { + dev_err(&pdev->dev, "Invalid clock configuration\n"); + return -EINVAL; + } + + core_clk = devm_clk_get(&pdev->dev, "rtc_sys_clk"); + if (IS_ERR(core_clk)) { + dev_err(&pdev->dev, "failed to get rtc sys clk\n"); + return PTR_ERR(core_clk); + } + clk_prepare_enable(core_clk); + + aml_rtc_init(&pdev->dev, rtc); + + device_init_wakeup(&pdev->dev, 1); + platform_set_drvdata(pdev, rtc); + + rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtc->rtc_dev)) + return PTR_ERR(rtc->rtc_dev); + + ret = devm_request_irq(&pdev->dev, rtc->irq, aml_rtc_handler, + IRQF_ONESHOT, "aml-rtc alarm", rtc); + if (ret) { + dev_err(&pdev->dev, "IRQ%d request failed, ret = %d\n", + rtc->irq, ret); + return ret; + } + + rtc->rtc_dev->ops = &aml_rtc_ops; + rtc->rtc_dev->range_min = 0; + rtc->rtc_dev->range_max = U32_MAX; + + ret = rtc_add_group(rtc->rtc_dev, &aml_rtc_sysfs_files); + if (ret) { + dev_err(&pdev->dev, "Failed to create sysfs group: %d\n", ret); + return ret; + } + + return devm_rtc_register_device(rtc->rtc_dev); +} + +static int aml_rtc_suspend(struct device *dev) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + + if (device_may_wakeup(dev)) + enable_irq_wake(rtc->irq); + + return 0; +} + +static int aml_rtc_resume(struct device *dev) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + + if (device_may_wakeup(dev)) + disable_irq_wake(rtc->irq); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(aml_rtc_pm_ops, + aml_rtc_suspend, aml_rtc_resume); + +static const struct aml_rtc_config a5_rtc_config = { +}; + +static const struct aml_rtc_config a4_rtc_config = { + .gray_stored = true, +}; + +static const struct of_device_id aml_rtc_device_id[] = { + { + .compatible = "amlogic,a4-rtc", + .data = &a4_rtc_config, + }, + { + .compatible = "amlogic,a5-rtc", + .data = &a5_rtc_config, + }, +}; +MODULE_DEVICE_TABLE(of, aml_rtc_device_id); + +static struct platform_driver aml_rtc_driver = { + .probe = aml_rtc_probe, + .driver = { + .name = "aml-rtc", + .of_match_table = of_match_ptr(aml_rtc_device_id), + .pm = &aml_rtc_pm_ops, + }, +}; + +module_platform_driver(aml_rtc_driver); +MODULE_DESCRIPTION("Amlogic RTC driver"); +MODULE_AUTHOR("Yiting Deng "); +MODULE_LICENSE("GPL"); -- 2.37.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D39DC531DC for ; Fri, 23 Aug 2024 09:22:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References: Message-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=P+xVH8Sk+sqHYgpe4d7cL7WMw/F3YEmEtNXSpcBkux4=; b=dLTdDUDExuEfNJ uaaBILJWFqA5SRO67wJWkkxHX5vcZswaZ4YodY3kgJrNB6vvW8VA0TREbkvzlGD+XCn3ZFTo1K/nk sqpSrv+DAmLC8A8FEGjYt4ijJxlFEMHkxrpLyWwxWEBNCyfnmz4hMGAuDmcUcR/8+pMe93XW3kCPc QOtwZuw/dtIzSHbx7O1NKJw30uCiLHcrfSVJeQoa1HfQJ2RywcENInVb0CbSA/RBPo49OxNdSPPvo G4wNCwuq7jbi8kNu8l7mZqrB66A7VMK0e9QdoiuuH9bFo6Utsqu97EnEhfjEpF/ClX6oP3oHHzYcQ QY11CERVH+tQxMm095lA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1shQUv-0000000G5Wd-3zx8; Fri, 23 Aug 2024 09:22:21 +0000 Received: from nyc.source.kernel.org ([147.75.193.91]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1shQSS-0000000G4qW-3soK for linux-amlogic@lists.infradead.org; Fri, 23 Aug 2024 09:19:51 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 48959A42636; Fri, 23 Aug 2024 09:19:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 68B90C4AF11; Fri, 23 Aug 2024 09:19:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724404787; bh=MXFzkmpRC0PZZsntldVxcz/toh6gIkYoENkSIz0o4VI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=I/3WHDQJtjILZqmXApfVNcn/YSSjAO0mJjgJiD7WAJHsSkZuPx+eg+SqGEKLy69pZ mrSFI0dyKwxFnsL2XwgPjjCAlUSUArQVMq0bwcuWA6v8T8j1wXLfoVtYM8YGg33yc+ bsNuPiVHO8TAtcWl+6iTmmpEOkemkP05PFH4B9DuYvvmcffl0KkRwJk0FTl0xHIcug wYBK3wf4xgFdrGaFKtAGH2TouHEt7DA7w6nK+uWl7+j1z7Ba2gFFjoSR/2uCQ039Ac mysV7htHayG1AoNqozJ+EnEV3xyLBjShOn6edtbfCkvy5UcYu5rcYv9ojK0AFnwM5e pWM6WUkwp4jYw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5926AC5472D; Fri, 23 Aug 2024 09:19:47 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 23 Aug 2024 17:19:45 +0800 Subject: [PATCH 2/3] rtc: support for the Amlogic on-chip RTC MIME-Version: 1.0 Message-Id: <20240823-rtc-v1-2-6f70381da283@amlogic.com> References: <20240823-rtc-v1-0-6f70381da283@amlogic.com> In-Reply-To: <20240823-rtc-v1-0-6f70381da283@amlogic.com> To: Yiting Deng , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724404784; l=18890; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=uTuv7es8G0Sz0X0k67EdKdNym5NaaQd1YXkQ9wf35M4=; b=ZUApP7jYDGTGxZXNq3YBnYVcupXPyw+l7ig8jWctgOzmcEMQhKeVw3E/OjXJet7lZoRLyVJpm qozz4edsE9+DWo3n2AnMzK0F7Ze7cxR4oX2cQOMJeykgwdT5KrQY81e X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240823_021949_236355_4DD7A6C9 X-CRM114-Status: GOOD ( 22.84 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: xianwei.zhao@amlogic.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org RnJvbTogWWl0aW5nIERlbmcgPHlpdGluZy5kZW5nQGFtbG9naWMuY29tPgoKU3VwcG9ydCBmb3Ig dGhlIG9uLWNoaXAgUlRDIGZvdW5kIGluIHNvbWUgb2YgQW1sb2dpYydzIFNvQ3Mgc3VjaCBhcyB0 aGUKQTExM0wyIGFuZCBBMTEzWDIuCgpTaWduZWQtb2ZmLWJ5OiBZaXRpbmcgRGVuZyA8eWl0aW5n LmRlbmdAYW1sb2dpYy5jb20+ClNpZ25lZC1vZmYtYnk6IFhpYW53ZWkgWmhhbyA8eGlhbndlaS56 aGFvQGFtbG9naWMuY29tPgotLS0KIGRyaXZlcnMvcnRjL0tjb25maWcgICAgICAgfCAgMTIgKwog ZHJpdmVycy9ydGMvTWFrZWZpbGUgICAgICB8ICAgMSArCiBkcml2ZXJzL3J0Yy9ydGMtYW1sb2dp Yy5jIHwgNTg5ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysK IDMgZmlsZXMgY2hhbmdlZCwgNjAyIGluc2VydGlvbnMoKykKCmRpZmYgLS1naXQgYS9kcml2ZXJz L3J0Yy9LY29uZmlnIGIvZHJpdmVycy9ydGMvS2NvbmZpZwppbmRleCAyYTk1YjA1OTgyYWQuLjBk ZDA0MjcwMWMzYiAxMDA2NDQKLS0tIGEvZHJpdmVycy9ydGMvS2NvbmZpZworKysgYi9kcml2ZXJz L3J0Yy9LY29uZmlnCkBAIC0yMDQzLDQgKzIwNDMsMTYgQEAgY29uZmlnIFJUQ19EUlZfU1NEMjAy RAogCSAgVGhpcyBkcml2ZXIgY2FuIGFsc28gYmUgYnVpbHQgYXMgYSBtb2R1bGUsIGlmIHNvLCB0 aGUgbW9kdWxlCiAJICB3aWxsIGJlIGNhbGxlZCAicnRjLXNzZDIweGQiLgogCitjb25maWcgUlRD X0RSVl9BTUxPR0lDCisJdHJpc3RhdGUgIkFtbG9naWMgUlRDIgorCWRlcGVuZHMgb24gQVJDSF9N RVNPTiB8fCBDT01QSUxFX1RFU1QKKwlzZWxlY3QgUkVHTUFQX01NSU8KKwlkZWZhdWx0IHkKKwlo ZWxwCisJICBJZiB5b3Ugc2F5IHllcyBoZXJlIHlvdSBnZXQgc3VwcG9ydCBmb3IgdGhlIFJUQyBi bG9jayBvbiB0aGUKKwkgIEFtbG9naWMgQTExM0wyKEE0KSBhbmQgQTExM1gyKEE1KSBTb0NzLgor CisJICBUaGlzIGRyaXZlciBjYW4gYWxzbyBiZSBidWlsdCBhcyBhIG1vZHVsZS4gSWYgc28sIHRo ZSBtb2R1bGUKKwkgIHdpbGwgYmUgY2FsbGVkICJydGMtYW1sb2dpYyIuCisKIGVuZGlmICMgUlRD X0NMQVNTCmRpZmYgLS1naXQgYS9kcml2ZXJzL3J0Yy9NYWtlZmlsZSBiL2RyaXZlcnMvcnRjL01h a2VmaWxlCmluZGV4IDMwMDRlMzcyZjI1Zi4uZDRhNTZkZGI0MjQ2IDEwMDY0NAotLS0gYS9kcml2 ZXJzL3J0Yy9NYWtlZmlsZQorKysgYi9kcml2ZXJzL3J0Yy9NYWtlZmlsZQpAQCAtMjYsNiArMjYs NyBAQCBvYmotJChDT05GSUdfUlRDX0RSVl9BQkI1WkVTMykJKz0gcnRjLWFiLWI1emUtczMubwog b2JqLSQoQ09ORklHX1JUQ19EUlZfQUJFT1o5KQkrPSBydGMtYWItZW96OS5vCiBvYmotJChDT05G SUdfUlRDX0RSVl9BQlg4MFgpCSs9IHJ0Yy1hYng4MHgubwogb2JqLSQoQ09ORklHX1JUQ19EUlZf QUMxMDApCSs9IHJ0Yy1hYzEwMC5vCitvYmotJChDT05GSUdfUlRDX0RSVl9BTUxPR0lDKQkrPSBy dGMtYW1sb2dpYy5vCiBvYmotJChDT05GSUdfUlRDX0RSVl9BUk1BREEzOFgpCSs9IHJ0Yy1hcm1h ZGEzOHgubwogb2JqLSQoQ09ORklHX1JUQ19EUlZfQVMzNzIyKQkrPSBydGMtYXMzNzIyLm8KIG9i ai0kKENPTkZJR19SVENfRFJWX0FTTTkyNjApCSs9IHJ0Yy1hc205MjYwLm8KZGlmZiAtLWdpdCBh L2RyaXZlcnMvcnRjL3J0Yy1hbWxvZ2ljLmMgYi9kcml2ZXJzL3J0Yy9ydGMtYW1sb2dpYy5jCm5l dyBmaWxlIG1vZGUgMTAwNjQ0CmluZGV4IDAwMDAwMDAwMDAwMC4uN2M2ODFhMjMyMGQzCi0tLSAv ZGV2L251bGwKKysrIGIvZHJpdmVycy9ydGMvcnRjLWFtbG9naWMuYwpAQCAtMCwwICsxLDU4OSBA QAorLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IChHUEwtMi4wLW9ubHkgT1IgTUlUKQorLyoK KyAqIENvcHlyaWdodCAoQykgMjAyNCBBbWxvZ2ljLCBJbmMuIEFsbCByaWdodHMgcmVzZXJ2ZWQK KyAqIEF1dGhvcjogWWl0aW5nIERlbmcgPHlpdGluZy5kZW5nQGFtbG9naWMuY29tPgorICovCisK KyNpbmNsdWRlIDxsaW51eC9tb2R1bGUuaD4KKyNpbmNsdWRlIDxsaW51eC9wbGF0Zm9ybV9kZXZp Y2UuaD4KKyNpbmNsdWRlIDxsaW51eC9yZWdtYXAuaD4KKyNpbmNsdWRlIDxsaW51eC9iaXRmaWVs ZC5oPgorI2luY2x1ZGUgPGxpbnV4L3J0Yy5oPgorI2luY2x1ZGUgPGxpbnV4L2Nsay5oPgorI2lu Y2x1ZGUgPGxpbnV4L2Nsay1wcm92aWRlci5oPgorI2luY2x1ZGUgPGxpbnV4L3RpbWU2NC5oPgor I2luY2x1ZGUgPGxpbnV4L2RlbGF5Lmg+CisKKy8qIHJ0YyBvc2NpbGxhdG9yIHJhdGUgKi8KKyNk ZWZpbmUgT1NDXzMySwkJCSgzMjc2OCkKKyNkZWZpbmUgT1NDXzI0TQkJCSgyNDAwMDAwMCkKKwor I2RlZmluZSBSVENfQ1RSTAkJKDB4MCA8PCAyKQkJLyogQ29udHJvbCBSVEMgKi8KKyNkZWZpbmUg UlRDX0FMUk0wX0VOCQlCSVQoMCkKKyNkZWZpbmUgUlRDX09TQ19TRUwJCUJJVCg4KQorI2RlZmlu ZSBSVENfRU5BQkxFCQlCSVQoMTIpCisKKyNkZWZpbmUgUlRDX0NPVU5URVJfUkVHCQkoMHgxIDw8 IDIpCQkvKiBQcm9ncmFtIFJUQyBjb3VudGVyIGluaXRpYWwgdmFsdWUgKi8KKworI2RlZmluZSBS VENfQUxBUk0wX1JFRwkJKDB4MiA8PCAyKQkJLyogUHJvZ3JhbSBSVEMgYWxhcm0wIHZhbHVlICov CisKKyNkZWZpbmUgUlRDX1NFQ19BREpVU1RfUkVHCSgweDYgPDwgMikJCS8qIENvbnRyb2wgc2Vj b25kLWJhc2VkIHRpbWluZyBhZGp1c3RtZW50ICovCisjZGVmaW5lIFJUQ19NQVRDSF9DT1VOVEVS CUdFTk1BU0soMTgsIDApCisjZGVmaW5lIFJUQ19TRUNfQURKVVNUX0NUUkwJR0VOTUFTSygyMCwg MTkpCisjZGVmaW5lIFJUQ19BREpfVkFMSUQJCUJJVCgyMykKKyNkZWZpbmUgUlRDX0RJVjI1Nl9B REpfVkFMCUJJVCgyNCkKKyNkZWZpbmUgUlRDX0RJVjI1Nl9BREpfRFNSCUJJVCgyNSkKKworI2Rl ZmluZSBSVENfSU5UX01BU0sJCSgweDggPDwgMikJCS8qIFJUQyBpbnRlcnJ1cHQgbWFzayAqLwor I2RlZmluZSBSVENfQUxSTTBfSVJRX01TSwlCSVQoMCkKKworI2RlZmluZSBSVENfSU5UX0NMUgkJ KDB4OSA8PCAyKQkJLyogQ2xlYXIgUlRDIGludGVycnVwdCAqLworI2RlZmluZSBSVENfQUxSTTBf SVJRX0NMUglCSVQoMCkKKworI2RlZmluZSBSVENfT1NDSU5fQ1RSTDAJCSgweGEgPDwgMikJCS8q IENvbnRyb2wgUlRDIGNsayBmcm9tIDI0TSAqLworI2RlZmluZSBSVENfT1NDSU5fQ1RSTDEJCSgw eGIgPDwgMikJCS8qIENvbnRyb2wgUlRDIGNsayBmcm9tIDI0TSAqLworI2RlZmluZSBSVENfT1ND SU5fSU5fRU4JCUJJVCgzMSkKKyNkZWZpbmUgUlRDX09TQ0lOX09VVF9DRkcJR0VOTUFTSygyOSwg MjgpCisjZGVmaW5lIFJUQ19PU0NJTl9PVVRfTjBNMAlHRU5NQVNLKDExLCAwKQorI2RlZmluZSBS VENfT1NDSU5fT1VUX04xTTEJR0VOTUFTSygyMywgMTIpCisKKyNkZWZpbmUgUlRDX0lOVF9TVEFU VVMJCSgweGMgPDwgMikJCS8qIFJUQyBpbnRlcnJ1cHQgc3RhdHVzICovCisjZGVmaW5lIFJUQ19B TFJNMF9JUlFfU1RBVFVTCUJJVCgwKQorCisjZGVmaW5lIFJUQ19SRUFMX1RJTUUJCSgweGQgPDwg MikJCS8qIFJUQyB0aW1lIHZhbHVlICovCisKKyNkZWZpbmUgUlRDX09TQ0lOX09VVF8zMktfTjAJ MHgyZGMKKyNkZWZpbmUgUlRDX09TQ0lOX09VVF8zMktfTjEJMHgyZGIKKyNkZWZpbmUgUlRDX09T Q0lOX09VVF8zMktfTTAJMHgxCisjZGVmaW5lIFJUQ19PU0NJTl9PVVRfMzJLX00xCTB4MgorCitz dHJ1Y3QgYW1sX3J0Y19jb25maWcgeworCWJvb2wgZ3JheV9zdG9yZWQ7Cit9OworCitzdHJ1Y3Qg YW1sX3J0Y19kYXRhIHsKKwlzdHJ1Y3QgcmVnbWFwICptYXA7CisJc3RydWN0IHJ0Y19kZXZpY2Ug KnJ0Y19kZXY7CisJaW50IGlycTsKKwlzdHJ1Y3QgY2xrICpzY2xrOworCWNvbnN0IHN0cnVjdCBh bWxfcnRjX2NvbmZpZyAqY29uZmlnOworfTsKKworc3RhdGljIGNvbnN0IHN0cnVjdCByZWdtYXBf Y29uZmlnIGFtbF9ydGNfcmVnbWFwX2NvbmZpZyA9IHsKKwkucmVnX2JpdHMgPSAzMiwKKwkudmFs X2JpdHMgPSAzMiwKKwkucmVnX3N0cmlkZSA9IDQsCisJLm1heF9yZWdpc3RlciA9IFJUQ19SRUFM X1RJTUUsCit9OworCitzdGF0aWMgdTMyIGdyYXlfdG9fYmluYXJ5KHUzMiBncmF5KQoreworCXUz MiBiY2QgPSBncmF5OworCWludCBzaXplID0gc2l6ZW9mKGJjZCkgKiA4OworCWludCBpOworCisJ Zm9yIChpID0gMDsgKDEgPDwgaSkgPCBzaXplOyBpKyspCisJCWJjZCBePSBiY2QgPj4gKDEgPDwg aSk7CisKKwlyZXR1cm4gYmNkOworfQorCitzdGF0aWMgdTMyIGJpbmFyeV90b19ncmF5KHUzMiBi Y2QpCit7CisJcmV0dXJuIGJjZCBeIChiY2QgPj4gMSk7Cit9CisKK3N0YXRpYyB2b2lkIGFtbF9z ZXRfdGltZShzdHJ1Y3QgYW1sX3J0Y19kYXRhICpydGMsIHUzMiB0aW1lX3NlYykKK3sKKwlpZiAo cnRjLT5jb25maWctPmdyYXlfc3RvcmVkKQorCQl0aW1lX3NlYyA9IGJpbmFyeV90b19ncmF5KHRp bWVfc2VjKTsKKwlyZWdtYXBfd3JpdGUocnRjLT5tYXAsIFJUQ19DT1VOVEVSX1JFRywgdGltZV9z ZWMpOworfQorCitzdGF0aWMgdTMyIGFtbF9yZWFkX3RpbWUoc3RydWN0IGFtbF9ydGNfZGF0YSAq cnRjKQoreworCXUzMiB0aW1lX3NlYzsKKworCXJlZ21hcF9yZWFkKHJ0Yy0+bWFwLCBSVENfUkVB TF9USU1FLCAmdGltZV9zZWMpOworCWlmIChydGMtPmNvbmZpZy0+Z3JheV9zdG9yZWQpCisJCXRp bWVfc2VjID0gZ3JheV90b19iaW5hcnkodGltZV9zZWMpOworCXJldHVybiB0aW1lX3NlYzsKK30K Kworc3RhdGljIHUzMiBhbWxfcmVhZF9hbGFybShzdHJ1Y3QgYW1sX3J0Y19kYXRhICpydGMpCit7 CisJdTMyIGFsYXJtX3NlYzsKKworCXJlZ21hcF9yZWFkKHJ0Yy0+bWFwLCBSVENfQUxBUk0wX1JF RywgJmFsYXJtX3NlYyk7CisJaWYgKHJ0Yy0+Y29uZmlnLT5ncmF5X3N0b3JlZCkKKwkJYWxhcm1f c2VjID0gZ3JheV90b19iaW5hcnkoYWxhcm1fc2VjKTsKKwlyZXR1cm4gYWxhcm1fc2VjOworfQor CitzdGF0aWMgdm9pZCBhbWxfc2V0X2FsYXJtKHN0cnVjdCBhbWxfcnRjX2RhdGEgKnJ0YywgdTMy IGFsYXJtX3NlYykKK3sKKwlpZiAocnRjLT5jb25maWctPmdyYXlfc3RvcmVkKQorCQlhbGFybV9z ZWMgPSBiaW5hcnlfdG9fZ3JheShhbGFybV9zZWMpOworCXJlZ21hcF93cml0ZShydGMtPm1hcCwg UlRDX0FMQVJNMF9SRUcsIGFsYXJtX3NlYyk7Cit9CisKK3N0YXRpYyBpbnQgYW1sX3J0Y19yZWFk X3RpbWUoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgcnRjX3RpbWUgKnRtKQoreworCXN0cnVj dCBhbWxfcnRjX2RhdGEgKnJ0YyA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOworCXUzMiB0aW1lX3Nl YzsKKworCXRpbWVfc2VjID0gYW1sX3JlYWRfdGltZShydGMpOworCXJ0Y190aW1lNjRfdG9fdG0o dGltZV9zZWMsIHRtKTsKKwlkZXZfZGJnKGRldiwgIiVzOiByZWFkIHRpbWUgPSAldXNcbiIsIF9f ZnVuY19fLCB0aW1lX3NlYyk7CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGljIGludCBhbWxfcnRj X3NldF90aW1lKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IHJ0Y190aW1lICp0bSkKK3sKKwlz dHJ1Y3QgYW1sX3J0Y19kYXRhICpydGMgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsKKwl1MzIgdGlt ZV9zZWM7CisKKwl0aW1lX3NlYyA9IHJ0Y190bV90b190aW1lNjQodG0pOworCWFtbF9zZXRfdGlt ZShydGMsIHRpbWVfc2VjKTsKKwlkZXZfZGJnKGRldiwgIiVzOiBzZXQgdGltZSA9ICV1c1xuIiwg X19mdW5jX18sIHRpbWVfc2VjKTsKKworCXJldHVybiAwOworfQorCitzdGF0aWMgaW50IGFtbF9y dGNfc2V0X2FsYXJtKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IHJ0Y193a2Fscm0gKmFsYXJt KQoreworCXN0cnVjdCBhbWxfcnRjX2RhdGEgKnJ0YyA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOwor CXRpbWU2NF90IGFsYXJtX3NlYzsKKworCWlmIChhbGFybS0+ZW5hYmxlZCkgeworCQlyZWdtYXBf dXBkYXRlX2JpdHMocnRjLT5tYXAsIFJUQ19DVFJMLAorCQkJCSAgIFJUQ19BTFJNMF9FTiwgUlRD X0FMUk0wX0VOKTsKKwkJcmVnbWFwX3VwZGF0ZV9iaXRzKHJ0Yy0+bWFwLCBSVENfSU5UX01BU0ss CisJCQkJICAgUlRDX0FMUk0wX0lSUV9NU0ssIDApOworCisJCWFsYXJtX3NlYyA9IHJ0Y190bV90 b190aW1lNjQoJmFsYXJtLT50aW1lKTsKKwkJaWYgKGFsYXJtX3NlYyA+IFUzMl9NQVgpIHsKKwkJ CWRldl9lcnIoZGV2LCAiYWxhcm0gdmFsdWUgaW52YWxpZCFcbiIpOworCQkJcmV0dXJuIC1FSU5W QUw7CisJCX0KKwkJYW1sX3NldF9hbGFybShydGMsIGFsYXJtX3NlYyk7CisJfQorCWRldl9kYmco ZGV2LCAiJXM6IGFsYXJtLT5lbmFibGVkPSVkIGFsYXJtX3NldD0lbGxkc1xuIiwgX19mdW5jX18s CisJCWFsYXJtLT5lbmFibGVkLCBhbGFybV9zZWMpOworCisJcmV0dXJuIDA7Cit9CisKK3N0YXRp YyBpbnQgYW1sX3J0Y19yZWFkX2FsYXJtKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IHJ0Y193 a2Fscm0gKmFsYXJtKQoreworCXN0cnVjdCBhbWxfcnRjX2RhdGEgKnJ0YyA9IGRldl9nZXRfZHJ2 ZGF0YShkZXYpOworCXUzMiBhbGFybV9zZWM7CisJdTMyIHJlZ192YWw7CisJaW50IGFsYXJtX2Vu YWJsZSwgYWxhcm1fbWFzazsKKworCWFsYXJtX3NlYyA9IGFtbF9yZWFkX2FsYXJtKHJ0Yyk7CisJ cnRjX3RpbWU2NF90b190bShhbGFybV9zZWMsICZhbGFybS0+dGltZSk7CisKKwlyZWdtYXBfcmVh ZChydGMtPm1hcCwgUlRDX0NUUkwsICZyZWdfdmFsKTsKKwlhbGFybV9lbmFibGUgPSBGSUVMRF9H RVQoUlRDX0FMUk0wX0VOLCByZWdfdmFsKTsKKworCXJlZ21hcF9yZWFkKHJ0Yy0+bWFwLCBSVENf SU5UX01BU0ssICZyZWdfdmFsKTsKKwlhbGFybV9tYXNrID0gRklFTERfR0VUKFJUQ19BTFJNMF9J UlFfTVNLLCByZWdfdmFsKTsKKworCWFsYXJtLT5lbmFibGVkID0gKGFsYXJtX2VuYWJsZSAmJiAh YWxhcm1fbWFzaykgPyAxIDogMDsKKwlkZXZfZGJnKGRldiwgIiVzOiBhbGFybS0+ZW5hYmxlZD0l ZCBhbGFybT0ldXNcbiIsIF9fZnVuY19fLAorCQlhbGFybS0+ZW5hYmxlZCwgYWxhcm1fc2VjKTsK KworCXJldHVybiAwOworfQorCitzdGF0aWMgaW50IGFtbF9ydGNfYWxhcm1fZW5hYmxlKHN0cnVj dCBkZXZpY2UgKmRldiwgdW5zaWduZWQgaW50IGVuYWJsZWQpCit7CisJc3RydWN0IGFtbF9ydGNf ZGF0YSAqcnRjID0gZGV2X2dldF9kcnZkYXRhKGRldik7CisKKwlpZiAoZW5hYmxlZCkgeworCQly ZWdtYXBfdXBkYXRlX2JpdHMocnRjLT5tYXAsIFJUQ19DVFJMLAorCQkJCSAgIFJUQ19BTFJNMF9F TiwgUlRDX0FMUk0wX0VOKTsKKwkJcmVnbWFwX3VwZGF0ZV9iaXRzKHJ0Yy0+bWFwLCBSVENfSU5U X01BU0ssCisJCQkJICAgUlRDX0FMUk0wX0lSUV9NU0ssIDApOworCX0gZWxzZSB7CisJCXJlZ21h cF91cGRhdGVfYml0cyhydGMtPm1hcCwgUlRDX0lOVF9NQVNLLAorCQkJCSAgIFJUQ19BTFJNMF9J UlFfTVNLLCBSVENfQUxSTTBfSVJRX01TSyk7CisJCXJlZ21hcF91cGRhdGVfYml0cyhydGMtPm1h cCwgUlRDX0NUUkwsCisJCQkJICAgUlRDX0FMUk0wX0VOLCAwKTsKKwl9CisKKwlyZXR1cm4gMDsK K30KKworc3RhdGljIGNvbnN0IHN0cnVjdCBydGNfY2xhc3Nfb3BzIGFtbF9ydGNfb3BzID0gewor CS5yZWFkX3RpbWUgPSBhbWxfcnRjX3JlYWRfdGltZSwKKwkuc2V0X3RpbWUgPSBhbWxfcnRjX3Nl dF90aW1lLAorCS5yZWFkX2FsYXJtID0gYW1sX3J0Y19yZWFkX2FsYXJtLAorCS5zZXRfYWxhcm0g PSBhbWxfcnRjX3NldF9hbGFybSwKKwkuYWxhcm1faXJxX2VuYWJsZSA9IGFtbF9ydGNfYWxhcm1f ZW5hYmxlLAorfTsKKworc3RhdGljIGlycXJldHVybl90IGFtbF9ydGNfaGFuZGxlcihpbnQgaXJx LCB2b2lkICpkYXRhKQoreworCXN0cnVjdCBhbWxfcnRjX2RhdGEgKnJ0YyA9IChzdHJ1Y3QgYW1s X3J0Y19kYXRhICopZGF0YTsKKworCXJlZ21hcF93cml0ZShydGMtPm1hcCwgUlRDX0FMQVJNMF9S RUcsIDApOworCXJlZ21hcF91cGRhdGVfYml0cyhydGMtPm1hcCwgUlRDX0lOVF9DTFIsCisJCQkg ICBSVENfQUxSTTBfSVJRX1NUQVRVUywgUlRDX0FMUk0wX0lSUV9TVEFUVVMpOworCisJcnRjX3Vw ZGF0ZV9pcnEocnRjLT5ydGNfZGV2LCAxLCBSVENfQUYgfCBSVENfSVJRRik7CisKKwlyZXR1cm4g SVJRX0hBTkRMRUQ7Cit9CisKK3N0YXRpYyBpbnQgYW1sX3J0Y19hZGp1c3Rfc2VjKHN0cnVjdCBk ZXZpY2UgKmRldiwgdTMyIG1hdGNoX2NvdW50ZXIsCisJCQkgICAgICBpbnQgb3BzLCBpbnQgZW5h YmxlKQoreworCXN0cnVjdCBhbWxfcnRjX2RhdGEgKnJ0YyA9IGRldl9nZXRfZHJ2ZGF0YShkZXYt PnBhcmVudCk7CisJdTMyIHJlZ192YWw7CisKKwlpZiAoIUZJRUxEX0ZJVChSVENfTUFUQ0hfQ09V TlRFUiwgbWF0Y2hfY291bnRlcikpIHsKKwkJcHJfZXJyKCIlczogaW52YWxpZCBtYXRjaF9jb3Vu dGVyXG4iLCBfX2Z1bmNfXyk7CisJCXJldHVybiAtRUlOVkFMOworCX0KKworCXJlZ192YWwgPSBG SUVMRF9QUkVQKFJUQ19TRUNfQURKVVNUX0NUUkwsIG9wcykKKwkJICB8IEZJRUxEX1BSRVAoUlRD X01BVENIX0NPVU5URVIsIG1hdGNoX2NvdW50ZXIpCisJCSAgfCBGSUVMRF9QUkVQKFJUQ19BREpf VkFMSUQsIGVuYWJsZSk7CisJLyogU2V0IHNlY19hZGp1c3RfY3RybCwgbWF0Y2hfY291bnRlciBh bmQgVmFsaWQgYWRqdXN0ICovCisJcmVnbWFwX3dyaXRlKHJ0Yy0+bWFwLCBSVENfU0VDX0FESlVT VF9SRUcsIHJlZ192YWwpOworCisJcmV0dXJuIDA7Cit9CisKK3N0YXRpYyBpbnQgYW1sX3J0Y19z ZXRfY2FsaWJyYXRpb24oc3RydWN0IGRldmljZSAqZGV2LCB1MzIgY2FsaWJyYXRpb24pCit7CisJ aW50IGNhbF9vcHMsIGVuYWJsZSwgbWF0Y2hfY291bnRlcjsKKwlpbnQgcmV0OworCisJbWF0Y2hf Y291bnRlciA9IEZJRUxEX0dFVChSVENfTUFUQ0hfQ09VTlRFUiwgY2FsaWJyYXRpb24pOworCWNh bF9vcHMgPSBGSUVMRF9HRVQoUlRDX1NFQ19BREpVU1RfQ1RSTCwgY2FsaWJyYXRpb24pOworCWVu YWJsZSA9IEZJRUxEX0dFVChSVENfQURKX1ZBTElELCBjYWxpYnJhdGlvbik7CisKKwlyZXQgPSBh bWxfcnRjX2FkanVzdF9zZWMoZGV2LCBtYXRjaF9jb3VudGVyLCBjYWxfb3BzLCBlbmFibGUpOwor CWRldl9kYmcoZGV2LCAiJXM6IFN1Y2Nlc3MgdG8gc3RvcmUgUlRDIGNhbGlicmF0aW9uIGF0dHJp YnV0ZVxuIiwKKwkJX19mdW5jX18pOworCisJcmV0dXJuIHJldDsKK30KKworc3RhdGljIGludCBh bWxfcnRjX2dldF9jYWxpYnJhdGlvbihzdHJ1Y3QgZGV2aWNlICpkZXYsIHUzMiAqY2FsaWJyYXRp b24pCit7CisJc3RydWN0IGFtbF9ydGNfZGF0YSAqcnRjID0gZGV2X2dldF9kcnZkYXRhKGRldi0+ cGFyZW50KTsKKwl1MzIgcmVnX3ZhbDsKKworCXJlZ21hcF9yZWFkKHJ0Yy0+bWFwLCBSVENfU0VD X0FESlVTVF9SRUcsICZyZWdfdmFsKTsKKwkqY2FsaWJyYXRpb24gPSBGSUVMRF9HRVQoUlRDX1NF Q19BREpVU1RfQ1RSTCB8IFJUQ19NQVRDSF9DT1VOVEVSLCByZWdfdmFsKTsKKwkvKiBCSVQgaXMg b25seSBVTCBkZWZpbmVk77yMYW5kIEdFTk1BU0sgaGFzIG5vIHR5cGUsIGl0cycgZG9ub3QgdXNl ZCB0b2dldGhlciAqLworCSpjYWxpYnJhdGlvbiB8PSBGSUVMRF9QUkVQKFJUQ19BREpfVkFMSUQs IEZJRUxEX0dFVChSVENfQURKX1ZBTElELCByZWdfdmFsKSk7CisKKwlyZXR1cm4gMDsKK30KKwor LyoqCisgKiBUaGUgY2FsaWJyYXRpb24gdmFsdWUgdHJhbnNmZXJyZWQgZnJvbSBidWYgdGFrZXMg Yml0WzE4OjBdIHRvIHJlcHJlc2VudAorICogbWF0Y2hfY291bnRlciwgd2hpbGUgdGFrZXMgYml0 WzIwOjE5XSB0byByZXByZXNlbnQgc2VjX2FkanVzdF9jdHJsLCBiaXRbMjNdCisgKiB0byByZXBy ZXNlbnQgYWRqX3ZhbGlkLiBlbmFibGUvZGlzYWJsZSBzZWNfYWRqdXN0X2N0cmwgYW5kIG1hdGNo X2NvdW50ZXIuCisgKiBAYnVmOiBTZXBhcmF0ZSBidWYgdG8gbWF0Y2hfY291bnRlciwgc2VjX2Fk anVzdF9jdHJsIGFuZCBhZGpfdmFsaWQKKyAqCSBtYXRjaF9jb3VudGVyOiBiaXRbMTg6MF0sIHZh bHVlIGlzIDAgfiAweDdmZmYKKyAqCSBzZWNfYWRqdXN0X2N0cmw6IGJpdFsyMDoxOV0sIHZhbHVl IGlzIDAgfiAyLiAzIHRvIGluc2VydCBhIHNlY29uZCBvbmNlIGV2ZXJ5CisgKgkgbWF0Y2hfY291 bnRlcisxIHNlY29uZHMsIDIgdG8gc3dhbGxvdyBhIHNlY29uZCBvbmNlIGV2ZXJ5IG1hdGNoX2Nv dW50ZXIrMSBzZWNvbmRzCisgKgkgMCBvciAxIHRvIG5vIGFkanVzdG1lbnQKKyAqCSBhZGpfdmFs aWQ6IGJpdFsyM10sIHZhbHVlIGlzIDAgb3IgMSwgMCB0byBkaXNhYmxlIHNlY19hZGp1c3RfY3Ry bCBhbmQKKyAqCSBtYXRjaF9jb3VudGVyLCBhbmQgMSB0byBlbmFibGUgdGhlbS4KKyAqLworc3Rh dGljIHNzaXplX3QgcnRjX2NhbGlicmF0aW9uX3N0b3JlKHN0cnVjdCBkZXZpY2UgKmRldiwKKwkJ CQkgICAgIHN0cnVjdCBkZXZpY2VfYXR0cmlidXRlICphdHRyLAorCQkJCSAgICAgY29uc3QgY2hh ciAqYnVmLCBzaXplX3QgY291bnQpCit7CisJaW50IHJldHZhbDsKKwlpbnQgY2FsaWJyYXRpb24g PSAwOworCisJaWYgKHNzY2FuZihidWYsICIgJWkgIiwgJmNhbGlicmF0aW9uKSAhPSAxKSB7CisJ CWRldl9lcnIoZGV2LCAiRmFpbGVkIHRvIHN0b3JlIFJUQyBjYWxpYnJhdGlvbiBhdHRyaWJ1dGVc biIpOworCQlyZXR1cm4gLUVJTlZBTDsKKwl9CisJcmV0dmFsID0gYW1sX3J0Y19zZXRfY2FsaWJy YXRpb24oZGV2LCBjYWxpYnJhdGlvbik7CisKKwlyZXR1cm4gcmV0dmFsID8gcmV0dmFsIDogY291 bnQ7Cit9CisKK3N0YXRpYyBzc2l6ZV90IHJ0Y19jYWxpYnJhdGlvbl9zaG93KHN0cnVjdCBkZXZp Y2UgKmRldiwKKwkJCQkgICAgc3RydWN0IGRldmljZV9hdHRyaWJ1dGUgKmF0dHIsIGNoYXIgKmJ1 ZikKK3sKKwlpbnQgIHJldHZhbCA9IDA7CisJdTMyICBjYWxpYnJhdGlvbiA9IDA7CisKKwlyZXR2 YWwgPSBhbWxfcnRjX2dldF9jYWxpYnJhdGlvbihkZXYsICZjYWxpYnJhdGlvbik7CisJaWYgKHJl dHZhbCA8IDApIHsKKwkJZGV2X2VycihkZXYsICJGYWlsZWQgdG8gcmVhZCBSVEMgY2FsaWJyYXRp b24gYXR0cmlidXRlXG4iKTsKKwkJc3ByaW50ZihidWYsICIwXG4iKTsKKwkJcmV0dXJuIHJldHZh bDsKKwl9CisKKwlyZXR1cm4gc3ByaW50ZihidWYsICIweCV4XG4iLCBjYWxpYnJhdGlvbik7Cit9 CitzdGF0aWMgREVWSUNFX0FUVFJfUlcocnRjX2NhbGlicmF0aW9uKTsKKworc3RhdGljIGludCBy dGNfc2V0X2RpdjI1Nl9hZGp1c3Qoc3RydWN0IGRldmljZSAqZGV2LCB1MzIgKnZhbHVlKQorewor CXN0cnVjdCBhbWxfcnRjX2RhdGEgKnJ0YyA9IGRldl9nZXRfZHJ2ZGF0YShkZXYtPnBhcmVudCk7 CisJdTMyIGRpdjI1Nl9hZGo7CisKKwlkaXYyNTZfYWRqID0gRklFTERfUFJFUChSVENfRElWMjU2 X0FESl9EU1IgfCBSVENfRElWMjU2X0FESl9WQUwsICp2YWx1ZSk7CisJLyoKKwkgKiBBT19SVENf U0VDX0FESlVTVF9SRUcgYml0IDI0IGluc2VydC9yZW1vdmUoMS8wKSBhIGRpdjI1NiBjeWNsZSwK KwkgKiBiaXQgMjUgdmFsaWQvaW52YWxpZCgxLzApIGRpdjI1Nl9hZGpfdmFsCisJICovCisJcmVn bWFwX3dyaXRlX2JpdHMocnRjLT5tYXAsIFJUQ19TRUNfQURKVVNUX1JFRywKKwkJCSAgUlRDX0RJ VjI1Nl9BREpfRFNSIHwgUlRDX0RJVjI1Nl9BREpfVkFMLCBkaXYyNTZfYWRqKTsKKwkvKiBydGMg bmVlZCBhYm91dCAzMG1zIHRvIGFkanVzdCBpdHMgdGltZSBhZnRlciB3cml0dGVuICovCisJbWRl bGF5KDMwKTsKKworCXJldHVybiAwOworfQorCitzdGF0aWMgaW50IHJ0Y19nZXRfZGl2MjU2X2Fk anVzdChzdHJ1Y3QgZGV2aWNlICpkZXYsIHUzMiAqdmFsdWUpCit7CisJc3RydWN0IGFtbF9ydGNf ZGF0YSAqcnRjID0gZGV2X2dldF9kcnZkYXRhKGRldi0+cGFyZW50KTsKKwl1MzIgcmVnX3ZhbDsK KworCXJlZ21hcF9yZWFkKHJ0Yy0+bWFwLCBSVENfU0VDX0FESlVTVF9SRUcsICZyZWdfdmFsKTsK KwkqdmFsdWUgPSBGSUVMRF9HRVQoUlRDX0RJVjI1Nl9BREpfRFNSIHwgUlRDX0RJVjI1Nl9BREpf VkFMLCByZWdfdmFsKTsKKworCXJldHVybiAwOworfQorCisvKioKKyAqIGRpdjI1NiBhZGp1c3Qg ZnVuY3Rpb24gaXMgY29udHJvbGxlZCB1c2luZyBiaXRbMjRdIGFuZCBiaXRbMjVdLgorICogdHJh bnNmZXJyZWQgYnVmIHRha2VzIGJpdFswXSB0byByZXByZXNlbnQgZGl2MjU2IGFkaiB2YWwsIGJp dFsxXQorICogdG8gcmVwcmVzZW50IGRpdjI1NiBhZGogZW5hYmxlL2Rpc2FibGUuIGRpdjI1NiBj eWNsZSBtZWFucyB0aGF0IGFkanVzdAorICogMS8zMjc2OC8yNTYgb25jZSBieSB3cml0dGVuIG9u Y2UsIGl0J3MgdmFsIGlzIGVxdWFsIHRvIDEvMTI4cworICogQGJ1ZjogMzogZW5hYmxlIGRpdjI1 NiBhZGp1c3QgYW5kIGluc2VydCBhIGRpdjI1NiBjeWNsZQorICoJIDI6IGVuYWJsZSBkaXYyNTYg YWRqdXN0IGFuZCByZW1vdmUgYSBkaXYyNTYgY3ljbGUKKyAqCSAxIG9yIDA6IGRpc2FibGUgZGl2 MjU2IGFkanVzdAorICovCitzdGF0aWMgc3NpemVfdCBydGNfZGl2MjU2X2FkanVzdF9zdG9yZShz dHJ1Y3QgZGV2aWNlICpkZXYsCisJCQkJICAgICAgIHN0cnVjdCBkZXZpY2VfYXR0cmlidXRlICph dHRyLAorCQkJCSAgICAgICBjb25zdCBjaGFyICpidWYsIHNpemVfdCBjb3VudCkKK3sKKwlpbnQg cmV0dmFsOworCXUzMiB2YWx1ZSA9IDA7CisKKwlpZiAoc3NjYW5mKGJ1ZiwgIiAlaSAiLCAmdmFs dWUpICE9IDEpIHsKKwkJZGV2X2VycihkZXYsICJGYWlsZWQgdG8gc3RvcmUgUlRDIGRpdjI1NiBh ZGp1c3QgYXR0cmlidXRlXG4iKTsKKwkJcmV0dXJuIC1FSU5WQUw7CisJfQorCXJldHZhbCA9IHJ0 Y19zZXRfZGl2MjU2X2FkanVzdChkZXYsICZ2YWx1ZSk7CisKKwlyZXR1cm4gcmV0dmFsID8gcmV0 dmFsIDogY291bnQ7Cit9CisKK3N0YXRpYyBzc2l6ZV90IHJ0Y19kaXYyNTZfYWRqdXN0X3Nob3co c3RydWN0IGRldmljZSAqZGV2LAorCQkJCSAgICAgIHN0cnVjdCBkZXZpY2VfYXR0cmlidXRlICph dHRyLCBjaGFyICpidWYpCit7CisJaW50IHJldHZhbCA9IDA7CisJdTMyIHZhbHVlID0gMDsKKwor CXJldHZhbCA9IHJ0Y19nZXRfZGl2MjU2X2FkanVzdChkZXYsICZ2YWx1ZSk7CisJaWYgKHJldHZh bCA8IDApIHsKKwkJZGV2X2VycihkZXYsICJGYWlsZWQgdG8gcmVhZCBSVEMgZGl2MjU2IGFkanVz dCBhdHRyaWJ1dGVcbiIpOworCQlzcHJpbnRmKGJ1ZiwgIjBcbiIpOworCQlyZXR1cm4gcmV0dmFs OworCX0KKworCXJldHVybiBzcHJpbnRmKGJ1ZiwgIjB4JXhcbiIsIHZhbHVlKTsKK30KK3N0YXRp YyBERVZJQ0VfQVRUUl9SVyhydGNfZGl2MjU2X2FkanVzdCk7CisKK3N0YXRpYyBzdHJ1Y3QgYXR0 cmlidXRlICphbWxfcnRjX2F0dHJzW10gPSB7CisJJmRldl9hdHRyX3J0Y19jYWxpYnJhdGlvbi5h dHRyLAorCSZkZXZfYXR0cl9ydGNfZGl2MjU2X2FkanVzdC5hdHRyLAorCU5VTEwsCit9OworCitz dGF0aWMgY29uc3Qgc3RydWN0IGF0dHJpYnV0ZV9ncm91cCBhbWxfcnRjX3N5c2ZzX2ZpbGVzID0g eworCS5hdHRycwk9IGFtbF9ydGNfYXR0cnMsCit9OworCitzdGF0aWMgdm9pZCBhbWxfcnRjX2lu aXQoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgYW1sX3J0Y19kYXRhICpydGMpCit7CisJdTMy IHJlZ192YWw7CisJdTMyIHJ0Y19lbmFibGU7CisKKwlyZWdtYXBfcmVhZChydGMtPm1hcCwgUlRD X0NUUkwsICZyZWdfdmFsKTsKKwlydGNfZW5hYmxlID0gRklFTERfR0VUKFJUQ19FTkFCTEUsIHJl Z192YWwpOworCWlmICghcnRjX2VuYWJsZSkgeworCQlpZiAoY2xrX2dldF9yYXRlKHJ0Yy0+c2Ns aykgPT0gT1NDXzI0TSkgeworCQkJLyogc2VsZWN0IDI0TSBvc2NpbGxhdG9yICovCisJCQlyZWdt YXBfdXBkYXRlX2JpdHMocnRjLT5tYXAsIFJUQ19DVFJMLCBSVENfT1NDX1NFTCwgUlRDX09TQ19T RUwpOworCisJCQkvKgorCQkJICogU2V0IFJUQyBvc2NpbGxhdG9yIHRvIGZyZXFfb3V0IHRvIGZy ZXFfaW4vKChOMCpNMCtOMSpNMSkvKE0wK00xKSkKKwkJCSAqIEVuYWJsZSBjbG9ja19pbiBnYXRl IG9mIG9zY2lsbGF0b3IgMjRNSHoKKwkJCSAqIFNldCBOMCB0byA3MzMsIE4xIHRvIDczMgorCQkJ ICovCisJCQlyZWdfdmFsID0gRklFTERfUFJFUChSVENfT1NDSU5fSU5fRU4sIDEpCisJCQkJICB8 IEZJRUxEX1BSRVAoUlRDX09TQ0lOX09VVF9DRkcsIDEpCisJCQkJICB8IEZJRUxEX1BSRVAoUlRD X09TQ0lOX09VVF9OME0wLCBSVENfT1NDSU5fT1VUXzMyS19OMCkKKwkJCQkgIHwgRklFTERfUFJF UChSVENfT1NDSU5fT1VUX04xTTEsIFJUQ19PU0NJTl9PVVRfMzJLX04xKTsKKwkJCXJlZ21hcF93 cml0ZV9iaXRzKHJ0Yy0+bWFwLCBSVENfT1NDSU5fQ1RSTDAsIFJUQ19PU0NJTl9JTl9FTgorCQkJ CQkgIHwgUlRDX09TQ0lOX09VVF9DRkcgfCBSVENfT1NDSU5fT1VUX04wTTAKKwkJCQkJICB8IFJU Q19PU0NJTl9PVVRfTjFNMSwgcmVnX3ZhbCk7CisKKwkJCS8qIFNldCBNMCB0byAyLCBNMSB0byAz LCBzbyBmcmVxX291dCA9IDMyNzY4IEh6Ki8KKwkJCXJlZ192YWwgPSBGSUVMRF9QUkVQKFJUQ19P U0NJTl9PVVRfTjBNMCwgUlRDX09TQ0lOX09VVF8zMktfTTApCisJCQkJICB8IEZJRUxEX1BSRVAo UlRDX09TQ0lOX09VVF9OMU0xLCBSVENfT1NDSU5fT1VUXzMyS19NMSk7CisJCQlyZWdtYXBfd3Jp dGVfYml0cyhydGMtPm1hcCwgUlRDX09TQ0lOX0NUUkwxLCBSVENfT1NDSU5fT1VUX04wTTAKKwkJ CQkJICB8IFJUQ19PU0NJTl9PVVRfTjFNMSwgcmVnX3ZhbCk7CisJCX0gZWxzZSB7CisJCQkvKiBz ZWxlY3QgMzJLIG9zY2lsbGF0b3IgKi8KKwkJCXJlZ21hcF93cml0ZV9iaXRzKHJ0Yy0+bWFwLCBS VENfQ1RSTCwgUlRDX09TQ19TRUwsIDApOworCQl9CisJCS8qIEVuYWJsZSBSVEMgKi8KKwkJcmVn bWFwX3dyaXRlX2JpdHMocnRjLT5tYXAsIFJUQ19DVFJMLCBSVENfRU5BQkxFLCBSVENfRU5BQkxF KTsKKwkJdXNsZWVwX3JhbmdlKDEwMCwgMjAwKTsKKwl9CisJcmVnbWFwX3dyaXRlX2JpdHMocnRj LT5tYXAsIFJUQ19JTlRfTUFTSywKKwkJCSAgUlRDX0FMUk0wX0lSUV9NU0ssIFJUQ19BTFJNMF9J UlFfTVNLKTsKKwlyZWdtYXBfd3JpdGVfYml0cyhydGMtPm1hcCwgUlRDX0NUUkwsIFJUQ19BTFJN MF9FTiwgMCk7Cit9CisKK3N0YXRpYyBpbnQgYW1sX3J0Y19wcm9iZShzdHJ1Y3QgcGxhdGZvcm1f ZGV2aWNlICpwZGV2KQoreworCXN0cnVjdCBhbWxfcnRjX2RhdGEgKnJ0YzsKKwl2b2lkIF9faW9t ZW0gKmJhc2U7CisJc3RydWN0IGNsayAqY29yZV9jbGs7CisJaW50IHJldCA9IDA7CisKKwlydGMg PSBkZXZtX2t6YWxsb2MoJnBkZXYtPmRldiwgc2l6ZW9mKCpydGMpLCBHRlBfS0VSTkVMKTsKKwlp ZiAoIXJ0YykKKwkJcmV0dXJuIC1FTk9NRU07CisKKwlydGMtPmNvbmZpZyA9IG9mX2RldmljZV9n ZXRfbWF0Y2hfZGF0YSgmcGRldi0+ZGV2KTsKKwlpZiAoIXJ0Yy0+Y29uZmlnKQorCQlyZXR1cm4g LUVOT0RFVjsKKworCWJhc2UgPSBkZXZtX3BsYXRmb3JtX2lvcmVtYXBfcmVzb3VyY2UocGRldiwg MCk7CisJaWYgKElTX0VSUihiYXNlKSkgeworCQlkZXZfZXJyKCZwZGV2LT5kZXYsICJyZXNvdXJj ZSBpb3JlbWFwIGZhaWxlZFxuIik7CisJCXJldHVybiBQVFJfRVJSKGJhc2UpOworCX0KKworCXJ0 Yy0+bWFwID0gZGV2bV9yZWdtYXBfaW5pdF9tbWlvKCZwZGV2LT5kZXYsIGJhc2UsICZhbWxfcnRj X3JlZ21hcF9jb25maWcpOworCWlmIChJU19FUlIocnRjLT5tYXApKSB7CisJCWRldl9lcnIoJnBk ZXYtPmRldiwgInJlZ21hcCBpbml0IGZhaWxlZFxuIik7CisJCXJldHVybiBQVFJfRVJSKHJ0Yy0+ bWFwKTsKKwl9CisKKwlydGMtPmlycSA9IHBsYXRmb3JtX2dldF9pcnEocGRldiwgMCk7CisJaWYg KHJ0Yy0+aXJxIDwgMCkKKwkJcmV0dXJuIHJ0Yy0+aXJxOworCisJcnRjLT5zY2xrID0gZGV2bV9j bGtfZ2V0KCZwZGV2LT5kZXYsICJydGNfb3NjIik7CisJaWYgKElTX0VSUihydGMtPnNjbGspKQor CQlyZXR1cm4gUFRSX0VSUihydGMtPnNjbGspOworCWlmIChjbGtfZ2V0X3JhdGUocnRjLT5zY2xr KSAhPSBPU0NfMzJLICYmIGNsa19nZXRfcmF0ZShydGMtPnNjbGspICE9IE9TQ18yNE0pIHsKKwkJ ZGV2X2VycigmcGRldi0+ZGV2LCAiSW52YWxpZCBjbG9jayBjb25maWd1cmF0aW9uXG4iKTsKKwkJ cmV0dXJuIC1FSU5WQUw7CisJfQorCisJY29yZV9jbGsgPSBkZXZtX2Nsa19nZXQoJnBkZXYtPmRl diwgInJ0Y19zeXNfY2xrIik7CisJaWYgKElTX0VSUihjb3JlX2NsaykpIHsKKwkJZGV2X2Vycigm cGRldi0+ZGV2LCAiZmFpbGVkIHRvIGdldCBydGMgc3lzIGNsa1xuIik7CisJCXJldHVybiBQVFJf RVJSKGNvcmVfY2xrKTsKKwl9CisJY2xrX3ByZXBhcmVfZW5hYmxlKGNvcmVfY2xrKTsKKworCWFt bF9ydGNfaW5pdCgmcGRldi0+ZGV2LCBydGMpOworCisJZGV2aWNlX2luaXRfd2FrZXVwKCZwZGV2 LT5kZXYsIDEpOworCXBsYXRmb3JtX3NldF9kcnZkYXRhKHBkZXYsIHJ0Yyk7CisKKwlydGMtPnJ0 Y19kZXYgPSBkZXZtX3J0Y19hbGxvY2F0ZV9kZXZpY2UoJnBkZXYtPmRldik7CisJaWYgKElTX0VS UihydGMtPnJ0Y19kZXYpKQorCQlyZXR1cm4gUFRSX0VSUihydGMtPnJ0Y19kZXYpOworCisJcmV0 ID0gZGV2bV9yZXF1ZXN0X2lycSgmcGRldi0+ZGV2LCBydGMtPmlycSwgYW1sX3J0Y19oYW5kbGVy LAorCQkJICAgICAgIElSUUZfT05FU0hPVCwgImFtbC1ydGMgYWxhcm0iLCBydGMpOworCWlmIChy ZXQpIHsKKwkJZGV2X2VycigmcGRldi0+ZGV2LCAiSVJRJWQgcmVxdWVzdCBmYWlsZWQsIHJldCA9 ICVkXG4iLAorCQkJcnRjLT5pcnEsIHJldCk7CisJCXJldHVybiByZXQ7CisJfQorCisJcnRjLT5y dGNfZGV2LT5vcHMgPSAmYW1sX3J0Y19vcHM7CisJcnRjLT5ydGNfZGV2LT5yYW5nZV9taW4gPSAw OworCXJ0Yy0+cnRjX2Rldi0+cmFuZ2VfbWF4ID0gVTMyX01BWDsKKworCXJldCA9IHJ0Y19hZGRf Z3JvdXAocnRjLT5ydGNfZGV2LCAmYW1sX3J0Y19zeXNmc19maWxlcyk7CisJaWYgKHJldCkgewor CQlkZXZfZXJyKCZwZGV2LT5kZXYsICJGYWlsZWQgdG8gY3JlYXRlIHN5c2ZzIGdyb3VwOiAlZFxu IiwgcmV0KTsKKwkJcmV0dXJuIHJldDsKKwl9CisKKwlyZXR1cm4gZGV2bV9ydGNfcmVnaXN0ZXJf ZGV2aWNlKHJ0Yy0+cnRjX2Rldik7Cit9CisKK3N0YXRpYyBpbnQgYW1sX3J0Y19zdXNwZW5kKHN0 cnVjdCBkZXZpY2UgKmRldikKK3sKKwlzdHJ1Y3QgYW1sX3J0Y19kYXRhICpydGMgPSBkZXZfZ2V0 X2RydmRhdGEoZGV2KTsKKworCWlmIChkZXZpY2VfbWF5X3dha2V1cChkZXYpKQorCQllbmFibGVf aXJxX3dha2UocnRjLT5pcnEpOworCisJcmV0dXJuIDA7Cit9CisKK3N0YXRpYyBpbnQgYW1sX3J0 Y19yZXN1bWUoc3RydWN0IGRldmljZSAqZGV2KQoreworCXN0cnVjdCBhbWxfcnRjX2RhdGEgKnJ0 YyA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOworCisJaWYgKGRldmljZV9tYXlfd2FrZXVwKGRldikp CisJCWRpc2FibGVfaXJxX3dha2UocnRjLT5pcnEpOworCisJcmV0dXJuIDA7Cit9CisKK3N0YXRp YyBTSU1QTEVfREVWX1BNX09QUyhhbWxfcnRjX3BtX29wcywKKwkJCSBhbWxfcnRjX3N1c3BlbmQs IGFtbF9ydGNfcmVzdW1lKTsKKworc3RhdGljIGNvbnN0IHN0cnVjdCBhbWxfcnRjX2NvbmZpZyBh NV9ydGNfY29uZmlnID0geworfTsKKworc3RhdGljIGNvbnN0IHN0cnVjdCBhbWxfcnRjX2NvbmZp ZyBhNF9ydGNfY29uZmlnID0geworCS5ncmF5X3N0b3JlZCA9IHRydWUsCit9OworCitzdGF0aWMg Y29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBhbWxfcnRjX2RldmljZV9pZFtdID0geworCXsKKwkJ LmNvbXBhdGlibGUgPSAiYW1sb2dpYyxhNC1ydGMiLAorCQkuZGF0YSA9ICZhNF9ydGNfY29uZmln LAorCX0sCisJeworCQkuY29tcGF0aWJsZSA9ICJhbWxvZ2ljLGE1LXJ0YyIsCisJCS5kYXRhID0g JmE1X3J0Y19jb25maWcsCisJfSwKK307CitNT0RVTEVfREVWSUNFX1RBQkxFKG9mLCBhbWxfcnRj X2RldmljZV9pZCk7CisKK3N0YXRpYyBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVyIGFtbF9ydGNfZHJp dmVyID0geworCS5wcm9iZSA9IGFtbF9ydGNfcHJvYmUsCisJLmRyaXZlciA9IHsKKwkJLm5hbWUg PSAiYW1sLXJ0YyIsCisJCS5vZl9tYXRjaF90YWJsZSA9IG9mX21hdGNoX3B0cihhbWxfcnRjX2Rl dmljZV9pZCksCisJCS5wbSA9ICZhbWxfcnRjX3BtX29wcywKKwl9LAorfTsKKworbW9kdWxlX3Bs YXRmb3JtX2RyaXZlcihhbWxfcnRjX2RyaXZlcik7CitNT0RVTEVfREVTQ1JJUFRJT04oIkFtbG9n aWMgUlRDIGRyaXZlciIpOworTU9EVUxFX0FVVEhPUigiWWl0aW5nIERlbmcgPHlpdGluZy5kZW5n QGFtbG9naWMuY29tPiIpOworTU9EVUxFX0xJQ0VOU0UoIkdQTCIpOwoKLS0gCjIuMzcuMQoKCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hbWxv Z2ljIG1haWxpbmcgbGlzdApsaW51eC1hbWxvZ2ljQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDov L2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hbWxvZ2ljCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B910114A0BD; Fri, 23 Aug 2024 09:19:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724404787; cv=none; b=snHzhlV3vTfqDcGxCVxgwXTjeDxR8FHh5aPJaRE9gW9mEd8f5X+th9DIhfWQs9nZhvT9LZukyq5MC+5EFznx5cpvx/LX7oeBBC+erOUCwKh/oiYr8UFsldOYCWYiBvzEhs3PZMfbVuzStRyHMJC3PpVXARWmnSwO8k72D0HSKs4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724404787; c=relaxed/simple; bh=MXFzkmpRC0PZZsntldVxcz/toh6gIkYoENkSIz0o4VI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NN7opiJTje6VQgGu9GZZRIbYh58y6HNQSHFO2vYw/COuK/Q/UTinPUzmR6Mg+SPRZfEVvAKPY6WhrDv2LqUTcemj5R78LjJl5IBEIiMZcoNXNe7pFoSyQKlZgM/Jui0+Mkw8mPz4vO+tafFyuAOuFkL/3QGDOk0NHGpDSjixFZo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I/3WHDQJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I/3WHDQJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 68B90C4AF11; Fri, 23 Aug 2024 09:19:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724404787; bh=MXFzkmpRC0PZZsntldVxcz/toh6gIkYoENkSIz0o4VI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=I/3WHDQJtjILZqmXApfVNcn/YSSjAO0mJjgJiD7WAJHsSkZuPx+eg+SqGEKLy69pZ mrSFI0dyKwxFnsL2XwgPjjCAlUSUArQVMq0bwcuWA6v8T8j1wXLfoVtYM8YGg33yc+ bsNuPiVHO8TAtcWl+6iTmmpEOkemkP05PFH4B9DuYvvmcffl0KkRwJk0FTl0xHIcug wYBK3wf4xgFdrGaFKtAGH2TouHEt7DA7w6nK+uWl7+j1z7Ba2gFFjoSR/2uCQ039Ac mysV7htHayG1AoNqozJ+EnEV3xyLBjShOn6edtbfCkvy5UcYu5rcYv9ojK0AFnwM5e pWM6WUkwp4jYw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5926AC5472D; Fri, 23 Aug 2024 09:19:47 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 23 Aug 2024 17:19:45 +0800 Subject: [PATCH 2/3] rtc: support for the Amlogic on-chip RTC Precedence: bulk X-Mailing-List: linux-rtc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20240823-rtc-v1-2-6f70381da283@amlogic.com> References: <20240823-rtc-v1-0-6f70381da283@amlogic.com> In-Reply-To: <20240823-rtc-v1-0-6f70381da283@amlogic.com> To: Yiting Deng , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724404784; l=18890; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=uTuv7es8G0Sz0X0k67EdKdNym5NaaQd1YXkQ9wf35M4=; b=ZUApP7jYDGTGxZXNq3YBnYVcupXPyw+l7ig8jWctgOzmcEMQhKeVw3E/OjXJet7lZoRLyVJpm qozz4edsE9+DWo3n2AnMzK0F7Ze7cxR4oX2cQOMJeykgwdT5KrQY81e X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Yiting Deng Support for the on-chip RTC found in some of Amlogic's SoCs such as the A113L2 and A113X2. Signed-off-by: Yiting Deng Signed-off-by: Xianwei Zhao --- drivers/rtc/Kconfig | 12 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-amlogic.c | 589 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 602 insertions(+) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2a95b05982ad..0dd042701c3b 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -2043,4 +2043,16 @@ config RTC_DRV_SSD202D This driver can also be built as a module, if so, the module will be called "rtc-ssd20xd". +config RTC_DRV_AMLOGIC + tristate "Amlogic RTC" + depends on ARCH_MESON || COMPILE_TEST + select REGMAP_MMIO + default y + help + If you say yes here you get support for the RTC block on the + Amlogic A113L2(A4) and A113X2(A5) SoCs. + + This driver can also be built as a module. If so, the module + will be called "rtc-amlogic". + endif # RTC_CLASS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 3004e372f25f..d4a56ddb4246 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_RTC_DRV_ABB5ZES3) += rtc-ab-b5ze-s3.o obj-$(CONFIG_RTC_DRV_ABEOZ9) += rtc-ab-eoz9.o obj-$(CONFIG_RTC_DRV_ABX80X) += rtc-abx80x.o obj-$(CONFIG_RTC_DRV_AC100) += rtc-ac100.o +obj-$(CONFIG_RTC_DRV_AMLOGIC) += rtc-amlogic.o obj-$(CONFIG_RTC_DRV_ARMADA38X) += rtc-armada38x.o obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o obj-$(CONFIG_RTC_DRV_ASM9260) += rtc-asm9260.o diff --git a/drivers/rtc/rtc-amlogic.c b/drivers/rtc/rtc-amlogic.c new file mode 100644 index 000000000000..7c681a2320d3 --- /dev/null +++ b/drivers/rtc/rtc-amlogic.c @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2024 Amlogic, Inc. All rights reserved + * Author: Yiting Deng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* rtc oscillator rate */ +#define OSC_32K (32768) +#define OSC_24M (24000000) + +#define RTC_CTRL (0x0 << 2) /* Control RTC */ +#define RTC_ALRM0_EN BIT(0) +#define RTC_OSC_SEL BIT(8) +#define RTC_ENABLE BIT(12) + +#define RTC_COUNTER_REG (0x1 << 2) /* Program RTC counter initial value */ + +#define RTC_ALARM0_REG (0x2 << 2) /* Program RTC alarm0 value */ + +#define RTC_SEC_ADJUST_REG (0x6 << 2) /* Control second-based timing adjustment */ +#define RTC_MATCH_COUNTER GENMASK(18, 0) +#define RTC_SEC_ADJUST_CTRL GENMASK(20, 19) +#define RTC_ADJ_VALID BIT(23) +#define RTC_DIV256_ADJ_VAL BIT(24) +#define RTC_DIV256_ADJ_DSR BIT(25) + +#define RTC_INT_MASK (0x8 << 2) /* RTC interrupt mask */ +#define RTC_ALRM0_IRQ_MSK BIT(0) + +#define RTC_INT_CLR (0x9 << 2) /* Clear RTC interrupt */ +#define RTC_ALRM0_IRQ_CLR BIT(0) + +#define RTC_OSCIN_CTRL0 (0xa << 2) /* Control RTC clk from 24M */ +#define RTC_OSCIN_CTRL1 (0xb << 2) /* Control RTC clk from 24M */ +#define RTC_OSCIN_IN_EN BIT(31) +#define RTC_OSCIN_OUT_CFG GENMASK(29, 28) +#define RTC_OSCIN_OUT_N0M0 GENMASK(11, 0) +#define RTC_OSCIN_OUT_N1M1 GENMASK(23, 12) + +#define RTC_INT_STATUS (0xc << 2) /* RTC interrupt status */ +#define RTC_ALRM0_IRQ_STATUS BIT(0) + +#define RTC_REAL_TIME (0xd << 2) /* RTC time value */ + +#define RTC_OSCIN_OUT_32K_N0 0x2dc +#define RTC_OSCIN_OUT_32K_N1 0x2db +#define RTC_OSCIN_OUT_32K_M0 0x1 +#define RTC_OSCIN_OUT_32K_M1 0x2 + +struct aml_rtc_config { + bool gray_stored; +}; + +struct aml_rtc_data { + struct regmap *map; + struct rtc_device *rtc_dev; + int irq; + struct clk *sclk; + const struct aml_rtc_config *config; +}; + +static const struct regmap_config aml_rtc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = RTC_REAL_TIME, +}; + +static u32 gray_to_binary(u32 gray) +{ + u32 bcd = gray; + int size = sizeof(bcd) * 8; + int i; + + for (i = 0; (1 << i) < size; i++) + bcd ^= bcd >> (1 << i); + + return bcd; +} + +static u32 binary_to_gray(u32 bcd) +{ + return bcd ^ (bcd >> 1); +} + +static void aml_set_time(struct aml_rtc_data *rtc, u32 time_sec) +{ + if (rtc->config->gray_stored) + time_sec = binary_to_gray(time_sec); + regmap_write(rtc->map, RTC_COUNTER_REG, time_sec); +} + +static u32 aml_read_time(struct aml_rtc_data *rtc) +{ + u32 time_sec; + + regmap_read(rtc->map, RTC_REAL_TIME, &time_sec); + if (rtc->config->gray_stored) + time_sec = gray_to_binary(time_sec); + return time_sec; +} + +static u32 aml_read_alarm(struct aml_rtc_data *rtc) +{ + u32 alarm_sec; + + regmap_read(rtc->map, RTC_ALARM0_REG, &alarm_sec); + if (rtc->config->gray_stored) + alarm_sec = gray_to_binary(alarm_sec); + return alarm_sec; +} + +static void aml_set_alarm(struct aml_rtc_data *rtc, u32 alarm_sec) +{ + if (rtc->config->gray_stored) + alarm_sec = binary_to_gray(alarm_sec); + regmap_write(rtc->map, RTC_ALARM0_REG, alarm_sec); +} + +static int aml_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + u32 time_sec; + + time_sec = aml_read_time(rtc); + rtc_time64_to_tm(time_sec, tm); + dev_dbg(dev, "%s: read time = %us\n", __func__, time_sec); + + return 0; +} + +static int aml_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + u32 time_sec; + + time_sec = rtc_tm_to_time64(tm); + aml_set_time(rtc, time_sec); + dev_dbg(dev, "%s: set time = %us\n", __func__, time_sec); + + return 0; +} + +static int aml_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + time64_t alarm_sec; + + if (alarm->enabled) { + regmap_update_bits(rtc->map, RTC_CTRL, + RTC_ALRM0_EN, RTC_ALRM0_EN); + regmap_update_bits(rtc->map, RTC_INT_MASK, + RTC_ALRM0_IRQ_MSK, 0); + + alarm_sec = rtc_tm_to_time64(&alarm->time); + if (alarm_sec > U32_MAX) { + dev_err(dev, "alarm value invalid!\n"); + return -EINVAL; + } + aml_set_alarm(rtc, alarm_sec); + } + dev_dbg(dev, "%s: alarm->enabled=%d alarm_set=%llds\n", __func__, + alarm->enabled, alarm_sec); + + return 0; +} + +static int aml_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + u32 alarm_sec; + u32 reg_val; + int alarm_enable, alarm_mask; + + alarm_sec = aml_read_alarm(rtc); + rtc_time64_to_tm(alarm_sec, &alarm->time); + + regmap_read(rtc->map, RTC_CTRL, ®_val); + alarm_enable = FIELD_GET(RTC_ALRM0_EN, reg_val); + + regmap_read(rtc->map, RTC_INT_MASK, ®_val); + alarm_mask = FIELD_GET(RTC_ALRM0_IRQ_MSK, reg_val); + + alarm->enabled = (alarm_enable && !alarm_mask) ? 1 : 0; + dev_dbg(dev, "%s: alarm->enabled=%d alarm=%us\n", __func__, + alarm->enabled, alarm_sec); + + return 0; +} + +static int aml_rtc_alarm_enable(struct device *dev, unsigned int enabled) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + + if (enabled) { + regmap_update_bits(rtc->map, RTC_CTRL, + RTC_ALRM0_EN, RTC_ALRM0_EN); + regmap_update_bits(rtc->map, RTC_INT_MASK, + RTC_ALRM0_IRQ_MSK, 0); + } else { + regmap_update_bits(rtc->map, RTC_INT_MASK, + RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK); + regmap_update_bits(rtc->map, RTC_CTRL, + RTC_ALRM0_EN, 0); + } + + return 0; +} + +static const struct rtc_class_ops aml_rtc_ops = { + .read_time = aml_rtc_read_time, + .set_time = aml_rtc_set_time, + .read_alarm = aml_rtc_read_alarm, + .set_alarm = aml_rtc_set_alarm, + .alarm_irq_enable = aml_rtc_alarm_enable, +}; + +static irqreturn_t aml_rtc_handler(int irq, void *data) +{ + struct aml_rtc_data *rtc = (struct aml_rtc_data *)data; + + regmap_write(rtc->map, RTC_ALARM0_REG, 0); + regmap_update_bits(rtc->map, RTC_INT_CLR, + RTC_ALRM0_IRQ_STATUS, RTC_ALRM0_IRQ_STATUS); + + rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return IRQ_HANDLED; +} + +static int aml_rtc_adjust_sec(struct device *dev, u32 match_counter, + int ops, int enable) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev->parent); + u32 reg_val; + + if (!FIELD_FIT(RTC_MATCH_COUNTER, match_counter)) { + pr_err("%s: invalid match_counter\n", __func__); + return -EINVAL; + } + + reg_val = FIELD_PREP(RTC_SEC_ADJUST_CTRL, ops) + | FIELD_PREP(RTC_MATCH_COUNTER, match_counter) + | FIELD_PREP(RTC_ADJ_VALID, enable); + /* Set sec_adjust_ctrl, match_counter and Valid adjust */ + regmap_write(rtc->map, RTC_SEC_ADJUST_REG, reg_val); + + return 0; +} + +static int aml_rtc_set_calibration(struct device *dev, u32 calibration) +{ + int cal_ops, enable, match_counter; + int ret; + + match_counter = FIELD_GET(RTC_MATCH_COUNTER, calibration); + cal_ops = FIELD_GET(RTC_SEC_ADJUST_CTRL, calibration); + enable = FIELD_GET(RTC_ADJ_VALID, calibration); + + ret = aml_rtc_adjust_sec(dev, match_counter, cal_ops, enable); + dev_dbg(dev, "%s: Success to store RTC calibration attribute\n", + __func__); + + return ret; +} + +static int aml_rtc_get_calibration(struct device *dev, u32 *calibration) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev->parent); + u32 reg_val; + + regmap_read(rtc->map, RTC_SEC_ADJUST_REG, ®_val); + *calibration = FIELD_GET(RTC_SEC_ADJUST_CTRL | RTC_MATCH_COUNTER, reg_val); + /* BIT is only UL defined，and GENMASK has no type, its' donot used together */ + *calibration |= FIELD_PREP(RTC_ADJ_VALID, FIELD_GET(RTC_ADJ_VALID, reg_val)); + + return 0; +} + +/** + * The calibration value transferred from buf takes bit[18:0] to represent + * match_counter, while takes bit[20:19] to represent sec_adjust_ctrl, bit[23] + * to represent adj_valid. enable/disable sec_adjust_ctrl and match_counter. + * @buf: Separate buf to match_counter, sec_adjust_ctrl and adj_valid + * match_counter: bit[18:0], value is 0 ~ 0x7fff + * sec_adjust_ctrl: bit[20:19], value is 0 ~ 2. 3 to insert a second once every + * match_counter+1 seconds, 2 to swallow a second once every match_counter+1 seconds + * 0 or 1 to no adjustment + * adj_valid: bit[23], value is 0 or 1, 0 to disable sec_adjust_ctrl and + * match_counter, and 1 to enable them. + */ +static ssize_t rtc_calibration_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int retval; + int calibration = 0; + + if (sscanf(buf, " %i ", &calibration) != 1) { + dev_err(dev, "Failed to store RTC calibration attribute\n"); + return -EINVAL; + } + retval = aml_rtc_set_calibration(dev, calibration); + + return retval ? retval : count; +} + +static ssize_t rtc_calibration_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval = 0; + u32 calibration = 0; + + retval = aml_rtc_get_calibration(dev, &calibration); + if (retval < 0) { + dev_err(dev, "Failed to read RTC calibration attribute\n"); + sprintf(buf, "0\n"); + return retval; + } + + return sprintf(buf, "0x%x\n", calibration); +} +static DEVICE_ATTR_RW(rtc_calibration); + +static int rtc_set_div256_adjust(struct device *dev, u32 *value) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev->parent); + u32 div256_adj; + + div256_adj = FIELD_PREP(RTC_DIV256_ADJ_DSR | RTC_DIV256_ADJ_VAL, *value); + /* + * AO_RTC_SEC_ADJUST_REG bit 24 insert/remove(1/0) a div256 cycle, + * bit 25 valid/invalid(1/0) div256_adj_val + */ + regmap_write_bits(rtc->map, RTC_SEC_ADJUST_REG, + RTC_DIV256_ADJ_DSR | RTC_DIV256_ADJ_VAL, div256_adj); + /* rtc need about 30ms to adjust its time after written */ + mdelay(30); + + return 0; +} + +static int rtc_get_div256_adjust(struct device *dev, u32 *value) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev->parent); + u32 reg_val; + + regmap_read(rtc->map, RTC_SEC_ADJUST_REG, ®_val); + *value = FIELD_GET(RTC_DIV256_ADJ_DSR | RTC_DIV256_ADJ_VAL, reg_val); + + return 0; +} + +/** + * div256 adjust function is controlled using bit[24] and bit[25]. + * transferred buf takes bit[0] to represent div256 adj val, bit[1] + * to represent div256 adj enable/disable. div256 cycle means that adjust + * 1/32768/256 once by written once, it's val is equal to 1/128s + * @buf: 3: enable div256 adjust and insert a div256 cycle + * 2: enable div256 adjust and remove a div256 cycle + * 1 or 0: disable div256 adjust + */ +static ssize_t rtc_div256_adjust_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int retval; + u32 value = 0; + + if (sscanf(buf, " %i ", &value) != 1) { + dev_err(dev, "Failed to store RTC div256 adjust attribute\n"); + return -EINVAL; + } + retval = rtc_set_div256_adjust(dev, &value); + + return retval ? retval : count; +} + +static ssize_t rtc_div256_adjust_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval = 0; + u32 value = 0; + + retval = rtc_get_div256_adjust(dev, &value); + if (retval < 0) { + dev_err(dev, "Failed to read RTC div256 adjust attribute\n"); + sprintf(buf, "0\n"); + return retval; + } + + return sprintf(buf, "0x%x\n", value); +} +static DEVICE_ATTR_RW(rtc_div256_adjust); + +static struct attribute *aml_rtc_attrs[] = { + &dev_attr_rtc_calibration.attr, + &dev_attr_rtc_div256_adjust.attr, + NULL, +}; + +static const struct attribute_group aml_rtc_sysfs_files = { + .attrs = aml_rtc_attrs, +}; + +static void aml_rtc_init(struct device *dev, struct aml_rtc_data *rtc) +{ + u32 reg_val; + u32 rtc_enable; + + regmap_read(rtc->map, RTC_CTRL, ®_val); + rtc_enable = FIELD_GET(RTC_ENABLE, reg_val); + if (!rtc_enable) { + if (clk_get_rate(rtc->sclk) == OSC_24M) { + /* select 24M oscillator */ + regmap_update_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, RTC_OSC_SEL); + + /* + * Set RTC oscillator to freq_out to freq_in/((N0*M0+N1*M1)/(M0+M1)) + * Enable clock_in gate of oscillator 24MHz + * Set N0 to 733, N1 to 732 + */ + reg_val = FIELD_PREP(RTC_OSCIN_IN_EN, 1) + | FIELD_PREP(RTC_OSCIN_OUT_CFG, 1) + | FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_N0) + | FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_N1); + regmap_write_bits(rtc->map, RTC_OSCIN_CTRL0, RTC_OSCIN_IN_EN + | RTC_OSCIN_OUT_CFG | RTC_OSCIN_OUT_N0M0 + | RTC_OSCIN_OUT_N1M1, reg_val); + + /* Set M0 to 2, M1 to 3, so freq_out = 32768 Hz*/ + reg_val = FIELD_PREP(RTC_OSCIN_OUT_N0M0, RTC_OSCIN_OUT_32K_M0) + | FIELD_PREP(RTC_OSCIN_OUT_N1M1, RTC_OSCIN_OUT_32K_M1); + regmap_write_bits(rtc->map, RTC_OSCIN_CTRL1, RTC_OSCIN_OUT_N0M0 + | RTC_OSCIN_OUT_N1M1, reg_val); + } else { + /* select 32K oscillator */ + regmap_write_bits(rtc->map, RTC_CTRL, RTC_OSC_SEL, 0); + } + /* Enable RTC */ + regmap_write_bits(rtc->map, RTC_CTRL, RTC_ENABLE, RTC_ENABLE); + usleep_range(100, 200); + } + regmap_write_bits(rtc->map, RTC_INT_MASK, + RTC_ALRM0_IRQ_MSK, RTC_ALRM0_IRQ_MSK); + regmap_write_bits(rtc->map, RTC_CTRL, RTC_ALRM0_EN, 0); +} + +static int aml_rtc_probe(struct platform_device *pdev) +{ + struct aml_rtc_data *rtc; + void __iomem *base; + struct clk *core_clk; + int ret = 0; + + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + + rtc->config = of_device_get_match_data(&pdev->dev); + if (!rtc->config) + return -ENODEV; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(&pdev->dev, "resource ioremap failed\n"); + return PTR_ERR(base); + } + + rtc->map = devm_regmap_init_mmio(&pdev->dev, base, &aml_rtc_regmap_config); + if (IS_ERR(rtc->map)) { + dev_err(&pdev->dev, "regmap init failed\n"); + return PTR_ERR(rtc->map); + } + + rtc->irq = platform_get_irq(pdev, 0); + if (rtc->irq < 0) + return rtc->irq; + + rtc->sclk = devm_clk_get(&pdev->dev, "rtc_osc"); + if (IS_ERR(rtc->sclk)) + return PTR_ERR(rtc->sclk); + if (clk_get_rate(rtc->sclk) != OSC_32K && clk_get_rate(rtc->sclk) != OSC_24M) { + dev_err(&pdev->dev, "Invalid clock configuration\n"); + return -EINVAL; + } + + core_clk = devm_clk_get(&pdev->dev, "rtc_sys_clk"); + if (IS_ERR(core_clk)) { + dev_err(&pdev->dev, "failed to get rtc sys clk\n"); + return PTR_ERR(core_clk); + } + clk_prepare_enable(core_clk); + + aml_rtc_init(&pdev->dev, rtc); + + device_init_wakeup(&pdev->dev, 1); + platform_set_drvdata(pdev, rtc); + + rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtc->rtc_dev)) + return PTR_ERR(rtc->rtc_dev); + + ret = devm_request_irq(&pdev->dev, rtc->irq, aml_rtc_handler, + IRQF_ONESHOT, "aml-rtc alarm", rtc); + if (ret) { + dev_err(&pdev->dev, "IRQ%d request failed, ret = %d\n", + rtc->irq, ret); + return ret; + } + + rtc->rtc_dev->ops = &aml_rtc_ops; + rtc->rtc_dev->range_min = 0; + rtc->rtc_dev->range_max = U32_MAX; + + ret = rtc_add_group(rtc->rtc_dev, &aml_rtc_sysfs_files); + if (ret) { + dev_err(&pdev->dev, "Failed to create sysfs group: %d\n", ret); + return ret; + } + + return devm_rtc_register_device(rtc->rtc_dev); +} + +static int aml_rtc_suspend(struct device *dev) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + + if (device_may_wakeup(dev)) + enable_irq_wake(rtc->irq); + + return 0; +} + +static int aml_rtc_resume(struct device *dev) +{ + struct aml_rtc_data *rtc = dev_get_drvdata(dev); + + if (device_may_wakeup(dev)) + disable_irq_wake(rtc->irq); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(aml_rtc_pm_ops, + aml_rtc_suspend, aml_rtc_resume); + +static const struct aml_rtc_config a5_rtc_config = { +}; + +static const struct aml_rtc_config a4_rtc_config = { + .gray_stored = true, +}; + +static const struct of_device_id aml_rtc_device_id[] = { + { + .compatible = "amlogic,a4-rtc", + .data = &a4_rtc_config, + }, + { + .compatible = "amlogic,a5-rtc", + .data = &a5_rtc_config, + }, +}; +MODULE_DEVICE_TABLE(of, aml_rtc_device_id); + +static struct platform_driver aml_rtc_driver = { + .probe = aml_rtc_probe, + .driver = { + .name = "aml-rtc", + .of_match_table = of_match_ptr(aml_rtc_device_id), + .pm = &aml_rtc_pm_ops, + }, +}; + +module_platform_driver(aml_rtc_driver); +MODULE_DESCRIPTION("Amlogic RTC driver"); +MODULE_AUTHOR("Yiting Deng "); +MODULE_LICENSE("GPL"); -- 2.37.1