From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEDD6C5321D for ; Mon, 26 Aug 2024 15:32:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sibgL-0002Pl-UO; Mon, 26 Aug 2024 11:31:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sibfq-0000bB-UG for qemu-riscv@nongnu.org; Mon, 26 Aug 2024 11:30:39 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sibfm-0003ex-CG for qemu-riscv@nongnu.org; Mon, 26 Aug 2024 11:30:30 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-7143ae1b48fso2480188b3a.1 for ; Mon, 26 Aug 2024 08:30:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724686224; x=1725291024; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Me2VGPUEXV7YOq9Qji0+deQmkhrMet0QMl6ntOV33uw=; b=USXuF81LQmn4xiw51E6bu68/wWAppgcY1my/B/ec8Gm7rexhXcLnZHa/BmQHkRGbXM nJ7aQBH+mwevCgkJm8fHi/fsMf95RNkQKBkOp7Lw6D+G8rCixt9UX9GC+U9Q/ZpnIKK3 M1kuAWPNl36+pL6Ux3AIR1o8xObdGCC1LaO3LyeIXP6NwHdjb+T5j2Mx4icO9Eqa/AG9 Uxah5+BN/Y0YtO0bMAITi+fx+5cFUlwNmMGpXI0/bQpBUcnMWewrQGXRzIrsHyF1ixhu aQi29lYgCZWxztW/MmPy8+FlxBbhbOp/iGLhrvpB5gQAwncu0ilin/BX4cnJivt5i2we rpYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724686224; x=1725291024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Me2VGPUEXV7YOq9Qji0+deQmkhrMet0QMl6ntOV33uw=; b=eXqQKQv2RU75xOiPKCAiyNWVkVjGy90QzN1Yq2TVWzJfimd9lDhROv5qoeWRQK/m/o 1eLI3Q6zROrnR/pXty2PvVwovOIpRWRfGZpf+WQnRcY6D+H3RtrTCOWV2mVvbvOHJAYK Rx0nwRO+141KeKgsNMGx6Eiv1Fj0DzZNurPbx1b4/aVFV6eDOLmWzscAasUyxbbfI04N hb0ETFP36+R5b1FS4YrzPw6tvPbsTmaXKNr+nHXvQaoGGUaoVb+dN4Li6C/rGHlKxzGQ 8jJYxBnxY2xhcWlvq2dnQsUMn5J/Mqmj8o/DuQ3B09/HmO/Z/hgLmbznSGHhEzEKDC6e N8qg== X-Gm-Message-State: AOJu0Yy7/gADG/7jgneCoyWfHlc6rr6reLgu/vxSn0YxCz2bMQef3bsb 9I8o/37QxDC2DnC0/yLjm3zjoO1QVGONW6f7EGyIUD+rUECFwlGE1+wULK0/ZE1UQnqD2Bq8i0c 6 X-Google-Smtp-Source: AGHT+IFwOw5kp3XgTbFhJRYQIwFeEoS8rdxy9x5UXeI39UT3sPlDcioazsW120yFodYQ7cZKZkSrRw== X-Received: by 2002:a05:6a00:27a0:b0:70d:3337:7820 with SMTP id d2e1a72fcca58-71445d2dc44mr11632926b3a.8.1724686224137; Mon, 26 Aug 2024 08:30:24 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7143422eaabsm7396525b3a.12.2024.08.26.08.30.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 08:30:23 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, richard.henderson@linaro.org, kito.cheng@sifive.com, Deepak Gupta Subject: [PATCH v9 11/17] target/riscv: mmu changes for zicfiss shadow stack protection Date: Mon, 26 Aug 2024 08:29:43 -0700 Message-ID: <20240826152949.294506-12-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240826152949.294506-1-debug@rivosinc.com> References: <20240826152949.294506-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=debug@rivosinc.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org zicfiss protects shadow stack using new page table encodings PTE.W=0, PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not implemented or if shadow stack are not enabled. Loads on shadow stack memory are allowed while stores to shadow stack memory leads to access faults. Shadow stack accesses to RO memory leads to store page fault. To implement special nature of shadow stack memory where only selected stores (shadow stack stores from sspush) have to be allowed while rest of regular stores disallowed, new MMU TLB index is created for shadow stack. Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Reviewed-by: Richard Henderson --- target/riscv/cpu_helper.c | 37 +++++++++++++++++++++++++++++++------ target/riscv/internals.h | 3 +++ 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ca6d8f1f39..b10c3a35c4 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -892,6 +892,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, hwaddr ppn; int napot_bits = 0; target_ulong napot_mask; + bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE); + bool sstack_page = false; /* * Check if we should use the background registers for the two @@ -1100,21 +1102,36 @@ restart: return TRANSLATE_FAIL; } + target_ulong rwx = pte & (PTE_R | PTE_W | PTE_X); /* Check for reserved combinations of RWX flags. */ - switch (pte & (PTE_R | PTE_W | PTE_X)) { - case PTE_W: + switch (rwx) { case PTE_W | PTE_X: return TRANSLATE_FAIL; + case PTE_W: + /* if bcfi enabled, PTE_W is not reserved and shadow stack page */ + if (cpu_get_bcfien(env) && first_stage) { + sstack_page = true; + /* if ss index, read and write allowed. else only read allowed */ + rwx = is_sstack_idx ? PTE_R | PTE_W : PTE_R; + break; + } + return TRANSLATE_FAIL; + case PTE_R: + /* shadow stack writes to readonly memory are page faults */ + if (is_sstack_idx && access_type == MMU_DATA_STORE) { + return TRANSLATE_FAIL; + } + break; } int prot = 0; - if (pte & PTE_R) { + if (rwx & PTE_R) { prot |= PAGE_READ; } - if (pte & PTE_W) { + if (rwx & PTE_W) { prot |= PAGE_WRITE; } - if (pte & PTE_X) { + if (rwx & PTE_X) { bool mxr = false; /* @@ -1159,7 +1176,7 @@ restart: if (!((prot >> access_type) & 1)) { /* Access check failed */ - return TRANSLATE_FAIL; + return sstack_page ? TRANSLATE_PMP_FAIL : TRANSLATE_FAIL; } target_ulong updated_pte = pte; @@ -1346,9 +1363,17 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, break; case MMU_DATA_LOAD: cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; + /* shadow stack mis aligned accesses are access faults */ + if (mmu_idx & MMU_IDX_SS_WRITE) { + cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } break; case MMU_DATA_STORE: cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; + /* shadow stack mis aligned accesses are access faults */ + if (mmu_idx & MMU_IDX_SS_WRITE) { + cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + } break; default: g_assert_not_reached(); diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 0ac17bc5ad..ddbdee885b 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -30,12 +30,15 @@ * - U+2STAGE 0b100 * - S+2STAGE 0b101 * - S+SUM+2STAGE 0b110 + * - Shadow stack+U 0b1000 + * - Shadow stack+S 0b1001 */ #define MMUIdx_U 0 #define MMUIdx_S 1 #define MMUIdx_S_SUM 2 #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) +#define MMU_IDX_SS_WRITE (1 << 3) static inline int mmuidx_priv(int mmu_idx) { -- 2.44.0