From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu,
bmeng.cn@gmail.com, liwei1518@gmail.com,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com,
Deepak Gupta <debug@rivosinc.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v10 09/21] disas/riscv: enable `lpad` disassembly
Date: Tue, 27 Aug 2024 16:18:53 -0700 [thread overview]
Message-ID: <20240827231906.553327-10-debug@rivosinc.com> (raw)
In-Reply-To: <20240827231906.553327-1-debug@rivosinc.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 18 +++++++++++++++++-
disas/riscv.h | 2 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index c8364c2b07..c7c92acef7 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -974,6 +974,7 @@ typedef enum {
rv_op_amomaxu_h = 943,
rv_op_amocas_b = 944,
rv_op_amocas_h = 945,
+ rv_op_lpad = 946,
} rv_op;
/* register names */
@@ -2232,6 +2233,7 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "lpad", rv_codec_lp, rv_fmt_imm, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -2925,7 +2927,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 7: op = rv_op_andi; break;
}
break;
- case 5: op = rv_op_auipc; break;
+ case 5:
+ op = rv_op_auipc;
+ if (dec->cfg->ext_zicfilp &&
+ (((inst >> 7) & 0b11111) == 0b00000)) {
+ op = rv_op_lpad;
+ }
+ break;
case 6:
switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_addiw; break;
@@ -4482,6 +4490,11 @@ static uint32_t operand_tbl_index(rv_inst inst)
return ((inst << 54) >> 56);
}
+static uint32_t operand_lpl(rv_inst inst)
+{
+ return inst >> 12;
+}
+
/* decode operands */
static void decode_inst_operands(rv_decode *dec, rv_isa isa)
@@ -4869,6 +4882,9 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
dec->imm = sextract32(operand_rs2(inst), 0, 5);
dec->imm1 = operand_imm2(inst);
break;
+ case rv_codec_lp:
+ dec->imm = operand_lpl(inst);
+ break;
};
}
diff --git a/disas/riscv.h b/disas/riscv.h
index 16a08e4895..1182457aff 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -166,6 +166,7 @@ typedef enum {
rv_codec_r2_immhl,
rv_codec_r2_imm2_imm5,
rv_codec_fli,
+ rv_codec_lp,
} rv_codec;
/* structures */
@@ -228,6 +229,7 @@ enum {
#define rv_fmt_rs1_rs2 "O\t1,2"
#define rv_fmt_rd_imm "O\t0,i"
#define rv_fmt_rd_uimm "O\t0,Ui"
+#define rv_fmt_imm "O\ti"
#define rv_fmt_rd_offset "O\t0,o"
#define rv_fmt_rd_uoffset "O\t0,Uo"
#define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
--
2.44.0
next prev parent reply other threads:[~2024-08-27 23:23 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-27 23:18 [PATCH v10 00/21] riscv support for control flow integrity extensions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-08-28 0:04 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg Deepak Gupta
2024-08-28 0:10 ` Alistair Francis
2024-08-28 0:16 ` Deepak Gupta
2024-08-28 11:36 ` Richard Henderson
2024-08-27 23:18 ` [PATCH v10 03/21] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-27 23:59 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 04/21] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 05/21] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 06/21] target/riscv: additional code information for sw check Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 07/21] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 08/21] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-27 23:18 ` Deepak Gupta [this message]
2024-08-27 23:18 ` [PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-08-28 0:02 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 11/21] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-28 0:00 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 12/21] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 13/21] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 14/21] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 15/21] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 16/21] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 17/21] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 18/21] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 19/21] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 20/21] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 21/21] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
2024-08-27 23:22 ` [PATCH v10 00/21] riscv support for control flow integrity extensions Deepak Gupta
2024-08-28 0:02 ` Alistair Francis
2024-08-28 0:04 ` Deepak Gupta
2024-08-28 0:11 ` Alistair Francis
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