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From: Bjorn Helgaas <helgaas@kernel.org>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: linux-pci@vger.kernel.org,
	"Nicolas Saenz Julienne" <nsaenz@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Cyril Brulebois" <kibi@debian.org>,
	"Stanimir Varbanov" <svarbanov@suse.de>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
	"Florian Fainelli" <florian.fainelli@broadcom.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-rpi-kernel@lists.infradead.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 07/13] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific
Date: Mon, 2 Sep 2024 14:46:49 -0500	[thread overview]
Message-ID: <20240902194649.GA224705@bhelgaas> (raw)
In-Reply-To: <20240815225731.40276-8-james.quinlan@broadcom.com>

On Thu, Aug 15, 2024 at 06:57:20PM -0400, Jim Quinlan wrote:
> Do prepatory work for the 7712 SoC, which is introduced in a future commit.
> Our HW design has changed two register offsets for the 7712, where
> previously it was a common value for all Broadcom SOCs with PCIe cores.
> Specifically, the two offsets are to the registers HARD_DEBUG and
> INTR2_CPU_BASE.

> @@ -1499,12 +1502,16 @@ static const int pcie_offsets[] = {
>  	[RGR1_SW_INIT_1] = 0x9210,
>  	[EXT_CFG_INDEX]  = 0x9000,
>  	[EXT_CFG_DATA]   = 0x9004,
> +	[PCIE_HARD_DEBUG] = 0x4204,
> +	[PCIE_INTR2_CPU_BASE] = 0x4300,
>  };
>  
>  static const int pcie_offsets_bmips_7425[] = {
>  	[RGR1_SW_INIT_1] = 0x8010,
>  	[EXT_CFG_INDEX]  = 0x8300,
>  	[EXT_CFG_DATA]   = 0x8304,
> +	[PCIE_HARD_DEBUG] = 0x4204,
> +	[PCIE_INTR2_CPU_BASE] = 0x4300,
>  };
>  
>  static const struct pcie_cfg_data generic_cfg = {
> @@ -1539,6 +1546,8 @@ static const int pcie_offset_bcm7278[] = {
>  	[RGR1_SW_INIT_1] = 0xc010,
>  	[EXT_CFG_INDEX] = 0x9000,
>  	[EXT_CFG_DATA] = 0x9004,
> +	[PCIE_HARD_DEBUG] = 0x4204,
> +	[PCIE_INTR2_CPU_BASE] = 0x4300,
>  };

What's the organization scheme here?  We now have:

  static const int pcie_offsets[] = { ... };
  static const int pcie_offsets_bmips_7425[] = { ... };
  static const int pcie_offset_bcm7712[] = { ... };

  static const struct pcie_cfg_data generic_cfg = { ... };
  static const struct pcie_cfg_data bcm7425_cfg = { ... };
  static const struct pcie_cfg_data bcm7435_cfg = { ... };
  static const struct pcie_cfg_data bcm4908_cfg = { ... };

  static const int pcie_offset_bcm7278[] = { ... };

  static const struct pcie_cfg_data bcm7278_cfg = { ... };
  static const struct pcie_cfg_data bcm2711_cfg = { ... };
  static const struct pcie_cfg_data bcm7216_cfg = { ... };
  static const struct pcie_cfg_data bcm7712_cfg = { ... };

So we have pcie_offsets_bmips_7425[] and pcie_offset_bcm7712[] (with
gratuituously different "offset" vs "offsets") which are all together
before the pcie_cfg_data.

Then we have pcie_offset_bcm7278[] (again gratuitously different
"offset") separately, next to bcm7278_cfg.

It would be nice to pick one scheme and stick to it.

Also a seemingly random order of the pcie_cfg_data structs and
.compatible strings.

Also a little confusing to have "bmips_7425" and "bcm7425" associated
with the same chip.  I suppose there's historical reason for it, but I
don't think it's helpful in this usage.

>  static const struct pcie_cfg_data bcm7278_cfg = {
> -- 
> 2.17.1
> 

  reply	other threads:[~2024-09-02 19:46 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-15 22:57 [PATCH v6 00/13] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 01/13] dt-bindings: PCI: Change brcmstb maintainer and cleanup Jim Quinlan
2024-08-16  6:52   ` Krzysztof Kozlowski
2024-08-16 15:49   ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 02/13] dt-bindings: PCI: Use maxItems for reset controllers Jim Quinlan
2024-08-16  6:52   ` Krzysztof Kozlowski
2024-08-16 15:49   ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 03/13] dt-bindings: PCI: brcmstb: Add 7712 SoC description Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 04/13] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-08-16  7:02   ` Manivannan Sadhasivam
2024-08-16 15:50   ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 05/13] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-08-16  7:07   ` Manivannan Sadhasivam
2024-08-16 15:51   ` Florian Fainelli
2024-08-17 17:41   ` Stanimir Varbanov
2024-08-19 18:09     ` Jim Quinlan
2024-08-19 19:39       ` Stanimir Varbanov
2024-08-19 21:49         ` Jim Quinlan
2024-08-20 23:42           ` Stanimir Varbanov
2024-08-21 14:48             ` Jim Quinlan
2024-08-26 10:42               ` Stanimir Varbanov
2024-08-26 14:17                 ` Jim Quinlan
2024-08-27 12:27                   ` Stanimir Varbanov
2024-08-27 15:01                     ` Jim Quinlan
2024-09-01 18:04                       ` Krzysztof Wilczyński
2024-08-19 19:07     ` Florian Fainelli
2024-08-20 23:38       ` Stanimir Varbanov
2024-08-21 14:32         ` Jim Quinlan
2024-09-02 19:18   ` Bjorn Helgaas
2024-09-03 14:26     ` Jim Quinlan
2024-09-03 14:46       ` Krzysztof Wilczyński
2024-09-03 17:17         ` Bjorn Helgaas
2024-09-03 17:27           ` Krzysztof Wilczyński
2024-09-10 17:30       ` Jim Quinlan
2024-09-10 17:59         ` Bjorn Helgaas
2024-09-10 19:08           ` Krzysztof Wilczyński
2024-09-12 18:21           ` Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 06/13] PCI: brcmstb: Use swinit " Jim Quinlan
2024-08-16  7:08   ` Manivannan Sadhasivam
2024-08-16 15:51   ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 07/13] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-09-02 19:46   ` Bjorn Helgaas [this message]
2024-09-03 17:45     ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 08/13] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 09/13] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 10/13] PCI: brcmstb: Refactor for chips with many regular inbound windows Jim Quinlan
2024-08-16  7:11   ` Manivannan Sadhasivam
2024-08-16 15:57   ` Florian Fainelli
2024-08-17 16:45   ` Stanimir Varbanov
2024-09-02 20:45   ` Bjorn Helgaas
2024-08-15 22:57 ` [PATCH v6 11/13] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-08-16  7:14   ` Manivannan Sadhasivam
2024-08-15 22:57 ` [PATCH v6 12/13] PCI: brcmstb: Change field name from 'type' to 'soc_base' Jim Quinlan
2024-08-16  7:17   ` Manivannan Sadhasivam
2024-08-16 15:51   ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 13/13] PCI: brcmstb: Enable 7712 SOCs Jim Quinlan
2024-08-16  7:18 ` [PATCH v6 00/13] PCI: brcnstb: Enable STB 7712 SOC Manivannan Sadhasivam
2024-08-19 17:44   ` Jim Quinlan
2024-08-19 17:48     ` Florian Fainelli
2024-09-01 18:01 ` Krzysztof Wilczyński

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