From: Sean Anderson <sean.anderson@linux.dev>
To: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
netdev@vger.kernel.org
Cc: Michal Simek <michal.simek@amd.com>,
linux-arm-kernel@lists.infradead.org,
Ariane Keller <ariane.keller@tik.ee.ethz.ch>,
linux-kernel@vger.kernel.org,
Daniel Borkmann <daniel@iogearbox.net>,
Andy Chiu <andy.chiu@sifive.com>,
Sean Anderson <sean.anderson@linux.dev>
Subject: [PATCH net] net: xilinx: axienet: Fix IRQ coalescing packet count overflow
Date: Tue, 3 Sep 2024 14:00:59 -0400 [thread overview]
Message-ID: <20240903180059.4134461-1-sean.anderson@linux.dev> (raw)
If coalesce_count is greater than 255 it will not fit in the register and
will overflow. Clamp it to 255 for more-predictable results.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Fixes: 8a3b7a252dca ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 9aeb7b9f3ae4..5f27fc1c4375 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -252,7 +252,8 @@ static u32 axienet_usec_to_timer(struct axienet_local *lp, u32 coalesce_usec)
static void axienet_dma_start(struct axienet_local *lp)
{
/* Start updating the Rx channel control register */
- lp->rx_dma_cr = (lp->coalesce_count_rx << XAXIDMA_COALESCE_SHIFT) |
+ lp->rx_dma_cr = (min(lp->coalesce_count_rx, 255) <<
+ XAXIDMA_COALESCE_SHIFT) |
XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_ERROR_MASK;
/* Only set interrupt delay timer if not generating an interrupt on
* the first RX packet. Otherwise leave at 0 to disable delay interrupt.
@@ -264,7 +265,8 @@ static void axienet_dma_start(struct axienet_local *lp)
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr);
/* Start updating the Tx channel control register */
- lp->tx_dma_cr = (lp->coalesce_count_tx << XAXIDMA_COALESCE_SHIFT) |
+ lp->tx_dma_cr = (min(lp->coalesce_count_tx, 255) <<
+ XAXIDMA_COALESCE_SHIFT) |
XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_ERROR_MASK;
/* Only set interrupt delay timer if not generating an interrupt on
* the first TX packet. Otherwise leave at 0 to disable delay interrupt.
--
2.35.1.1320.gc452695387.dirty
next reply other threads:[~2024-09-03 18:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-03 18:00 Sean Anderson [this message]
2024-09-04 16:00 ` [PATCH net] net: xilinx: axienet: Fix IRQ coalescing packet count overflow Simon Horman
2024-09-05 14:34 ` Sean Anderson
2024-09-06 7:05 ` Simon Horman
2024-09-04 17:19 ` Pandey, Radhey Shyam
2024-09-05 14:55 ` Sean Anderson
2024-09-09 23:53 ` Sean Anderson
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