From: Conor Dooley <conor.dooley@microchip.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Conor Dooley <conor@kernel.org>, <devicetree@vger.kernel.org>,
<cyril.jean@microchip.com>,
<valentina.fernandezalanis@microchip.com>,
<nitin.deshpande@microchip.com>, Rob Herring <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [RFC v1] dt-bindings: add IP versioning document for Microchip FPGAs
Date: Mon, 9 Sep 2024 12:00:53 +0100 [thread overview]
Message-ID: <20240909-smock-displease-75d3fc0ff5da@wendy> (raw)
In-Reply-To: <4lsua4cxpxlla4i5rn7zmw3tvkbxz664a7as6jqy6qceljlj4x@ssev4fvuqz36>
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On Sat, Aug 31, 2024 at 08:45:06AM +0200, Krzysztof Kozlowski wrote:
> On Fri, Aug 30, 2024 at 05:00:40PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > This is a pretty rough document I conjured up in 5 minutes, to document
> > my expectations for compatible strings for both our FPGA IP blocks and
> > reference designs that we ship, a la the one that exists for SiFive IPs.
> > There's been some internal conversations lately about this naming etc,
> > so good to have something written down.
> >
>
> You can try to make it a schema. Take a peak at:
> Documentation/devicetree/bindings/arm/qcom-soc.yaml
Sure, I don't mind doing that - however given the breadth of microchip's
portfolio (and thus naming schemes) there may actually be little by way
of enforcement gained by making it into a binding. I'll give it a go and
see how permissive it ends up having to be.
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next prev parent reply other threads:[~2024-09-09 11:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-30 16:00 [RFC v1] dt-bindings: add IP versioning document for Microchip FPGAs Conor Dooley
2024-08-31 6:45 ` Krzysztof Kozlowski
2024-09-09 11:00 ` Conor Dooley [this message]
2024-09-03 14:59 ` Rob Herring
2024-09-09 10:58 ` Conor Dooley
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