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[185.176.79.56]) by mx.google.com with ESMTPS id ffacd0b85a97d-378956cffcdsi3870688f8f.891.2024.09.11.03.00.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Sep 2024 03:00:35 -0700 (PDT) Received-SPF: pass (google.com: domain of alireza.sanaee@huawei.com designates 185.176.79.56 as permitted sender) client-ip=185.176.79.56; Authentication-Results: mx.google.com; spf=pass (google.com: domain of alireza.sanaee@huawei.com designates 185.176.79.56 as permitted sender) smtp.mailfrom=alireza.sanaee@huawei.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4X3bYH5mCFz6K6DS; Wed, 11 Sep 2024 17:55:47 +0800 (CST) Received: from frapeml500003.china.huawei.com (unknown [7.182.85.28]) by mail.maildlp.com (Postfix) with ESMTPS id D4871140CB9; Wed, 11 Sep 2024 18:00:34 +0800 (CST) Received: from localhost (10.47.75.248) by frapeml500003.china.huawei.com (7.182.85.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Wed, 11 Sep 2024 12:00:33 +0200 Date: Wed, 11 Sep 2024 11:00:28 +0100 From: Alireza Sanaee To: Zhao Liu CC: "Daniel P .\" =?ISO-8859-1?Q?Berrang=E9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , Philippe =?ISO-8859-1?Q?Ma?= =?ISO-8859-1?Q?thieu-Daud=E9?= , Yanan Wang , Michael S.Tsirkin , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , Alex =?ISO-8859-1?Q?Benn=E9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma "@domain.invalid Subject: Re: [PATCH v2 6/7] i386/cpu: Update cache topology with machine's configuration Message-ID: <20240911110028.00001d3d@huawei.com> In-Reply-To: <20240908125920.1160236-7-zhao1.liu@intel.com> References: <20240908125920.1160236-1-zhao1.liu@intel.com> <20240908125920.1160236-7-zhao1.liu@intel.com> Organization: Huawei X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.47.75.248] X-ClientProxiedBy: lhrpeml500006.china.huawei.com (7.191.161.198) To frapeml500003.china.huawei.com (7.182.85.28) X-TUID: Uk2r2bNREj7v On Sun, 8 Sep 2024 20:59:19 +0800 Zhao Liu wrote: > User will configure smp cache topology via -machine smp-cache. > > For this case, update the x86 CPUs' cache topology with user's > configuration in MachineState. > > Signed-off-by: Zhao Liu > Tested-by: Yongwei Ma > --- > Changes since RFC v2: > * Used smp_cache array to override cache topology. > * Wrapped the updating into a function. > --- > target/i386/cpu.c | 39 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index e9f755000356..6d9f7dc0872a 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -7597,6 +7597,38 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) > cpu->hyperv_limits[2] = 0; > } > > +#ifndef CONFIG_USER_ONLY > +static void x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU > *cpu) +{ > + CPUX86State *env = &cpu->env; > + CpuTopologyLevel level; > + > + level = machine_get_cache_topo_level(ms, > CACHE_LEVEL_AND_TYPE_L1D); > + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { > + env->cache_info_cpuid4.l1d_cache->share_level = level; > + env->cache_info_amd.l1d_cache->share_level = level; > + } > + > + level = machine_get_cache_topo_level(ms, > CACHE_LEVEL_AND_TYPE_L1I); > + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { > + env->cache_info_cpuid4.l1i_cache->share_level = level; > + env->cache_info_amd.l1i_cache->share_level = level; > + } > + > + level = machine_get_cache_topo_level(ms, > CACHE_LEVEL_AND_TYPE_L2); > + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { > + env->cache_info_cpuid4.l2_cache->share_level = level; > + env->cache_info_amd.l2_cache->share_level = level; > + } > + > + level = machine_get_cache_topo_level(ms, > CACHE_LEVEL_AND_TYPE_L3); > + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { > + env->cache_info_cpuid4.l3_cache->share_level = level; > + env->cache_info_amd.l3_cache->share_level = level; > + } > +} > +#endif > + > static void x86_cpu_realizefn(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -7821,6 +7853,13 @@ static void x86_cpu_realizefn(DeviceState > *dev, Error **errp) > #ifndef CONFIG_USER_ONLY > MachineState *ms = MACHINE(qdev_get_machine()); > + > + /* > + * TODO: Add a SMPCompatProps.has_caches flag to avoid useless > Updates > + * if user didn't set smp_cache. > + */ Hi Zhao, Thanks for sending this patchset so quickly. I really appreciate the TODO already :) It also helps me avoid going through every single layer, especially when I want to avoid matching system registers in ARM, particularly when there's no description in the command line. > + x86_cpu_update_smp_cache_topo(ms, cpu); > + > qemu_register_reset(x86_cpu_machine_reset_cb, cpu); > > if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > > 1) {