From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, clg@kaod.org, fbarrat@linux.ibm.com,
npiggin@gmail.com, milesg@linux.ibm.com
Subject: [PATCH v3 02/14] pnv/xive2: Define OGEN field in the TIMA
Date: Thu, 12 Sep 2024 15:50:16 -0500 [thread overview]
Message-ID: <20240912205028.15854-3-kowal@linux.ibm.com> (raw)
In-Reply-To: <20240912205028.15854-1-kowal@linux.ibm.com>
From: Frederic Barrat <fbarrat@linux.ibm.com>
The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This
patch defines it.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/ppc/xive_regs.h | 1 +
hw/intc/xive.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 9d52d464d9..9062c6abf6 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -79,6 +79,7 @@
#define TM_INC 0x5 /* - + - + */
#define TM_AGE 0x6 /* - + - + */
#define TM_PIPR 0x7 /* - + - + */
+#define TM_OGEN 0xF /* - + - - */ /* P10 only */
#define TM_WORD0 0x0
#define TM_WORD1 0x4
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 2fb38e2102..136d82338a 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -742,6 +742,10 @@ void xive_tctx_reset(XiveTCTX *tctx)
tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF;
tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF;
tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF;
+ if (!(xive_presenter_get_config(tctx->xptr) &
+ XIVE_PRESENTER_GEN1_TIMA_OS)) {
+ tctx->regs[TM_QW1_OS + TM_OGEN] = 2;
+ }
/*
* Initialize PIPR to 0xFF to avoid phantom interrupts when the
--
2.43.0
next prev parent reply other threads:[~2024-09-12 20:52 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-12 20:50 [PATCH v3 00/14] XIVE2 changes for TIMA operations Michael Kowal
2024-09-12 20:50 ` [PATCH v3 01/14] pnv/xive: TIMA patch sets pre-req alignment and formatting changes Michael Kowal
2024-09-12 20:50 ` Michael Kowal [this message]
2024-09-12 20:50 ` [PATCH v3 03/14] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" Michael Kowal
2024-09-12 20:50 ` [PATCH v3 04/14] pnv/xive2: Support for "OS LGS Push" TIMA operation Michael Kowal
2024-09-12 20:50 ` [PATCH v3 05/14] ppc/xive2: Dump more NVP state with 'info pic' Michael Kowal
2024-09-12 20:50 ` [PATCH v3 06/14] ppc/xive2: Dump the VP-group and crowd tables " Michael Kowal
2024-09-12 20:50 ` [PATCH v3 07/14] ppc/xive2: Allow 1-byte write of Target field in TIMA Michael Kowal
2024-09-12 20:50 ` [PATCH v3 08/14] ppc/xive2: Support "Pull Thread Context to Register" operation Michael Kowal
2024-09-12 20:50 ` [PATCH v3 09/14] ppc/xive2: Change context/ring specific functions to be generic Michael Kowal
2024-09-13 13:10 ` Cédric Le Goater
2024-09-13 15:50 ` Mike Kowal
2024-09-12 20:50 ` [PATCH v3 10/14] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" Michael Kowal
2024-09-13 13:12 ` Cédric Le Goater
2024-09-12 20:50 ` [PATCH v3 11/14] pnv/xive: Add special handling for pool targets Michael Kowal
2024-09-12 20:50 ` [PATCH v3 12/14] pnv/xive: Update PIPR when updating CPPR Michael Kowal
2024-09-12 20:50 ` [PATCH v3 13/14] pnv/xive2: TIMA support for 8-byte OS context push for PHYP Michael Kowal
2024-09-12 20:50 ` [PATCH v3 14/14] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths Michael Kowal
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