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charset=us-ascii Content-Disposition: inline tree: https://github.com/Freescale/linux-fslc 6.6-2.0.x-imx head: ac32ba5fe66266329914d2020570364afe217bec commit: 3440db800daa934166a7135e4b671763ec5d3e41 [537/16788] LF-446 clk: imx: lpcg-scu: SW workaround for errata (e10858) config: arm64-randconfig-002-20240928 (https://download.01.org/0day-ci/archive/20240928/202409281741.4rhDN0AP-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 14.1.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240928/202409281741.4rhDN0AP-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202409281741.4rhDN0AP-lkp@intel.com/ All warnings (new ones prefixed by >>): drivers/clk/imx/clk-lpcg-scu.c: In function 'do_lpcg_workaround': >> drivers/clk/imx/clk-lpcg-scu.c:51:21: warning: variable 'reg1' set but not used [-Wunused-but-set-variable] 51 | u32 reg1; | ^~~~ vim +/reg1 +51 drivers/clk/imx/clk-lpcg-scu.c 44 45 /* e10858 -LPCG clock gating register synchronization errata */ 46 static void do_lpcg_workaround(u32 rate, void __iomem *reg, u32 val) 47 { 48 writel(val, reg); 49 50 if (rate >= 24000000 || rate == 0) { > 51 u32 reg1; 52 53 /* 54 * The time taken to access the LPCG registers from the AP core 55 * through the interconnect is longer than the minimum delay 56 * of 4 clock cycles required by the errata. 57 * Adding a readl will provide sufficient delay to prevent 58 * back-to-back writes. 59 */ 60 reg1 = readl(reg); 61 } else { 62 /* 63 * For clocks running below 24MHz, wait a minimum of 64 * 4 clock cycles. 65 */ 66 ndelay(4 * (DIV_ROUND_UP(1000000000, rate))); 67 } 68 } 69 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki