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charset=us-ascii Content-Disposition: inline tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v6.6_LTS_2024.1_update head: 5365c13a86998da06d845c918f849b30b8735538 commit: 1dfb4885eaa39fb3269b13eee7d97481c409b8bb [703/1001] arm64: zynqmp: Add/Update/Sync DTs for xilinx platforms config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20240930/202409302037.T7CIVVmx-lkp@intel.com/config) compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project 7773243d9916f98ba0ffce0c3a960e4aa9f03e81) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240930/202409302037.T7CIVVmx-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202409302037.T7CIVVmx-lkp@intel.com/ All warnings (new ones prefixed by >>): >> arch/arm64/boot/dts/xilinx/zynqmp-sc-vn-p-b2197-00-revA.dtso:183:2: warning: '/*' within block comment [-Wcomment] 183 | /* i2c_main_1 - u147 - j157 - disable translation, add 8 */ | ^ 1 warning generated. arch/arm64/boot/dts/xilinx/zynqmp-sc-vn-p-b2197-00-revA.dtso:15.6-133.3: Warning (avoid_unnecessary_addr_size): /fragment@0/__overlay__: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property vim +183 arch/arm64/boot/dts/xilinx/zynqmp-sc-vn-p-b2197-00-revA.dtso 134 135 &i2c1 { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */ 140 /* DC/SE eeprom at 0x52 */ 141 x_prc_eeprom: eeprom@52 { /* u4 - DC card identification - possible WP */ 142 compatible = "atmel,24c02"; 143 reg = <0x52>; 144 bootph-all; 145 }; 146 147 x_prc_tca9534: gpio@22 { /* u5 */ 148 compatible = "nxp,pca9534"; 149 reg = <0x22>; 150 gpio-controller; /* IRQ not connected */ 151 #gpio-cells = <2>; 152 gpio-line-names = "xprc_sw_1", "xprc_sw_2", "xprc_sw_3", "xprc_sw_4", 153 "", "", "", ""; 154 gtr-sel0 { 155 gpio-hog; 156 gpios = <0 0>; 157 input; /* FIXME add meaning */ 158 line-name = "xprc_sw_1"; 159 }; 160 gtr-sel1 { 161 gpio-hog; 162 gpios = <1 0>; 163 input; /* FIXME add meaning */ 164 line-name = "xprc_sw_1"; 165 }; 166 gtr-sel2 { 167 gpio-hog; 168 gpios = <2 0>; 169 input; /* FIXME add meaning */ 170 line-name = "xprc_sw_1"; 171 }; 172 gtr-sel3 { 173 gpio-hog; 174 gpios = <3 0>; 175 input; /* FIXME add meaning */ 176 line-name = "xprc_sw_1"; 177 }; 178 }; 179 180 /* FMC eeproms at 0x50/0x51 */ 181 /* via j3/j5 to 0x68 to u32/9FGV1006C 182 > 183 /* i2c_main_1 - u147 - j157 - disable translation, add 8 */ 184 /* J1 - OE for u43@55 + 8 - 161,132813MHz - QSFP56G_0 */ 185 qsfp56g_0_clk: clock-controller@5d { 186 compatible = "renesas,proxo-xp"; 187 reg = <0x5d>; 188 #clock-cells = <0>; 189 clock-output-names = "qsfp56g_0_clk"; 190 }; 191 192 /* J2 - OE for u41@57 + 8 - 322,265625MHz - QSFP56G_1 */ 193 qsfp56g_1_clk: clock-controller@5f { 194 compatible = "renesas,proxo-xp"; 195 reg = <0x5f>; 196 #clock-cells = <0>; 197 clock-output-names = "qsfp56g_1_clk"; 198 }; 199 200 /* J81 - OE for u115@50 + 8 - 320MHz - LPDDR5_C0 */ 201 lpddr5_c0_clk: clock-controller@58 { 202 compatible = "renesas,proxo-xp"; 203 reg = <0x58>; 204 #clock-cells = <0>; 205 clock-output-names = "lpddr5_c0_clk"; 206 }; 207 208 /* i2c_main_2 - u148 - j122 - disable translation, add 9 */ 209 /* J112 - OE for u63@50 + 9 - 320MHz - LPDDR5_C2 */ 210 lpddr5_c2_clk: clock-controller@59 { 211 compatible = "renesas,proxo-xp"; 212 reg = <0x59>; 213 #clock-cells = <0>; 214 clock-output-names = "lpddr5_c2_clk"; 215 }; 216 217 /* i2c_main_3 - u149 - j154 - disable translation, add 6 */ 218 /* J78 - OE for u116@50 + 6 - 320MHz - DDR5_UDIMM */ 219 ddr5_udimm_clk: clock-controller@56 { 220 compatible = "renesas,proxo-xp"; 221 reg = <0x56>; 222 #clock-cells = <0>; 223 clock-output-names = "ddr5_udimm_clk"; 224 }; 225 226 /* i2c_main_4 - u150 - j146 - disable translation, add 5 */ 227 /* J107 - OE for u39@50 + 5 - 33,3333MHz - PS_REFCLK */ 228 ps_refclk: clock-controller@55 { 229 compatible = "renesas,proxo-xp"; 230 reg = <0x55>; 231 #clock-cells = <0>; 232 clock-output-names = "ps_refclk"; 233 }; 234 235 /* i2c_main_5 - u1782 - j1798 - disable translation, add 7 */ 236 /* J77 - OE for u1783@50 + 7 - 320MHz - DDR4 */ 237 ddr4_clk: clock-controller@57 { 238 compatible = "renesas,proxo-xp"; 239 reg = <0x57>; 240 #clock-cells = <0>; 241 clock-output-names = "ddr4_clk"; 242 }; 243 244 /* LTC4316 - not wired XORH/XORL - FIXME */ 245 /* J3 gate - FIXME should be connected for SW handling */ 246 /* i2c_main_1 bus */ 247 i2c1_u32: clock-controller@68 { 248 compatible = "renesas,9fgv1006"; 249 reg = <0x68>; 250 }; 251 252 /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */ 253 /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */ 254 /* this should be SW controlable too */ 255 }; 256 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki