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[31.30.173.13]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f79c67c5csm39870425e9.0.2024.10.03.01.42.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 01:42:30 -0700 (PDT) Date: Thu, 3 Oct 2024 10:42:29 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: Tomasz Jeznach , Jason Chien , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, frank.chang@sifive.com, Sebastien Boeuf Subject: Re: [PATCH for-9.2 v6 03/12] hw/riscv: add RISC-V IOMMU base emulation Message-ID: <20241003-c4e8eae2c7f018797cec8b94@orel> References: <20240801154334.1009852-1-dbarboza@ventanamicro.com> <20240801154334.1009852-4-dbarboza@ventanamicro.com> <2912ffbe-0ae6-42b7-86b0-379e4c1db5c5@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Tue, Oct 01, 2024 at 09:05:52PM GMT, Daniel Henrique Barboza wrote: > > > On 10/1/24 8:28 PM, Tomasz Jeznach wrote: > > On Tue, Sep 3, 2024 at 4:46 AM Daniel Henrique Barboza > > wrote: > > > > > > > > > > > > On 8/26/24 11:18 PM, Tomasz Jeznach wrote: > > > > On Fri, Aug 23, 2024 at 5:42 AM Daniel Henrique Barboza > > > > wrote: > > > > > > > > > > > > > > > > > > > > On 8/20/24 12:16 PM, Jason Chien wrote: > > > > > > Hi Daniel, > > > > > > > > (...) > > > > > iotlb->target_as = &s->trap_as; > > > > > > > > I'd suggest fixing the missing en_s check, to enable proper handling of MSIP. > > > > > > The '!en_s' check was removed because it was breaking irqbypass. I'll let Drew explain > > > more about it since he's been working in the kernel support for this use case. > > > > > > > > > > Is the missing `!en_s` check still problematic? > > Re-reading the code I'd say it's required here to catch only GPAs if S > > stage is BARE, not untranslated IOVA. > > > Yeah, for some reason the existence of that check breaks irqbypass, removing > it fixes it. > > I don't think it has to do with the check per se, but perhaps with a missing > conditional to proper handle the irqbypass case. This is one of the TODOs that > we should look at later, in particular when the irqbypass support starts to > get reviewed in the kernel. Right. VFIO only uses S-stage to translate GPAs. When irqbypass support is added, as it is here [1] (which is a series I've been waiting to post as an RFC after the first round of IOMMU driver patches gets merged), then this '!en_s' check breaks MSI translations. Thanks, drew