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From: "Niklas Söderlund" <niklas.soderlund+renesas@ragnatech.se>
To: Stefan Eichenberger <eichest@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Dimitri Fedrau <dima.fedrau@gmail.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [net-next 3/3] net: phy: marvell-88q2xxx: Enable auto negotiation for mv88q2110
Date: Sat, 5 Oct 2024 13:08:34 +0200	[thread overview]
Message-ID: <20241005110834.GC3563898@ragnatech.se> (raw)
In-Reply-To: <ZvQKU02iGgcq5Mzp@eichest-laptop>

Hello Stefan,

On 2024-09-25 15:04:19 +0200, Stefan Eichenberger wrote:
> Hi Niklas,
> 
> On Sat, Sep 14, 2024 at 04:21:36PM +0200, Niklas Söderlund wrote:
> > Hello,
> > 
> > On 2024-09-14 16:00:01 +0200, Stefan Eichenberger wrote:
> > > Hi Niklas and Andrew,
> > > 
> > > I was able to do a first basic test on my setup. I'm using the MV88Q2110
> > > and connecting it to a Göpel media converter that I use as a reference.
> > 
> > Thanks for testing this work.
> > 
> > > However, with your patch applied, I can't get a link. When I set a fixed
> > > link speed of 1GBit/s and the media converter is configured as the
> > > master, I can normally do: 
> > > ethtool -s end1 speed 1000 master-slave forced-slave
> > > After that, the link came up. However, with the changes made, I can't do
> > > this anymore. Can you reproduce this in your setup?
> > 
> > Without this patch I can't bring up a 1GBit/s link at all, I can only 
> > setup a 100 MBit/s link with,
> > 
> >     ethtool -s eth1 speed 100 master-slave forced-slave
> > 
> > If I do the same with speed set to a 1000 I never get a link. That's why 
> > autoneg is a such a boon for me, as with that I do get a 1 Gbit/s link.
> > 
> > As you have the MV88Q2110 datasheets, can you check the register writes 
> > in mv88q2110_init_seq0 and mv88q2110_init_seq1 for sanity? Maybe 
> > something is not quiet right there, I have only been able to reveres 
> > engineer support for autoneg so it's quiet likely.
> 
> Unfortunately this registers are not documented in the datasheet.
> However, from the software initialization guide the following values
> would be correct for A1 and A2 devices (A0 does not need one write):
> static const struct mmd_val mv88q2110_init_seq1[] = {
> 	{ MDIO_MMD_PCS, 0xffde, 0x402f },
> 	{ MDIO_MMD_PCS, 0xfe2a, 0x3c3d},
> 	{ MDIO_MMD_PCS, 0xfe34, 0x4040 },
> 	{ MDIO_MMD_PCS, 0xfe4b, 0x9337},
> 	{ MDIO_MMD_PCS, 0xfe2a, 0x3c1d },
> 	{ MDIO_MMD_PCS, 0xfe34, 0x0040 },
> 	{ MDIO_MMD_AN, 0x8032, 0x0064 },
> 	{ MDIO_MMD_AN, 0x8031, 0x0a01 },
> 	{ MDIO_MMD_AN, 0x8031, 0x0c01 },
> 	{ MDIO_MMD_PCS, 0xFE0F, 0x0000 },
> 	{ MDIO_MMD_PCS, 0x800C, 0x0000 },
> 	{ MDIO_MMD_PCS, 0x801D, 0x0800 },
> 	{ MDIO_MMD_PCS, 0xfc00, 0x01c0 },
> 	{ MDIO_MMD_PCS, 0xfc17, 0x0425},
> 	{ MDIO_MMD_PCS, 0xfc94, 0x5470},
> 	{ MDIO_MMD_PCS, 0xfc95, 0x0055},
> 	{ MDIO_MMD_PCS, 0xfc19, 0x08d8},
> 	{ MDIO_MMD_PCS, 0xfc1a, 0x0110},
> 	{ MDIO_MMD_PCS, 0xfc1b, 0x0a10},
> 	{ MDIO_MMD_PCS, 0xfc3a, 0x2725},
> 	{ MDIO_MMD_PCS, 0xfc61, 0x2627},
> 	{ MDIO_MMD_PCS, 0xfc3b, 0x1612},
> 	{ MDIO_MMD_PCS, 0xfc62, 0x1c12},
> 	{ MDIO_MMD_PCS, 0xfc9d, 0x6367},
> 	{ MDIO_MMD_PCS, 0xfc9e, 0x8060},
> 	{ MDIO_MMD_PCS, 0xfc00, 0x01c8},
> 	{ MDIO_MMD_PCS, 0x8000, 0x0000},
> 	{ MDIO_MMD_PCS, 0x8016, 0x0011},
> 	{ MDIO_MMD_PCS, 0xfda3, 0x1800}, /* According to datahsheet not for Rev A0 */
> 	{ MDIO_MMD_PCS, 0xfe02, 0x00c0},
> 	{ MDIO_MMD_PCS, 0xffdb, 0x0010},
> 	{ MDIO_MMD_PCS, 0xfff3, 0x0020},
> 	{ MDIO_MMD_PCS, 0xfe40, 0x00a6},
> 	{ MDIO_MMD_PCS, 0xfe60, 0x0000},
> 	{ MDIO_MMD_PCS, 0xfe04, 0x0008},
> 	{ MDIO_MMD_PCS, 0xfe2a, 0x3c3d},
> 	{ MDIO_MMD_PCS, 0xfe4b, 0x9334},
> 	{ MDIO_MMD_PCS, 0xfc10, 0xf600},
> 	{ MDIO_MMD_PCS, 0xfc11, 0x073d},
> 	{ MDIO_MMD_PCS, 0xfc12, 0x000d},
> 	{ MDIO_MMD_PCS, 0xfc13, 0x0010},
> };
> 
> On my side, your values and the ones above are working.

Thanks for checking.

> 
> By the way, do you know why you only get between 800 and 850 Mbps? On my
> setup I see up to 930 Mbps in bidir mode. Just asking because maybe this
> is the reason why fixed speed doesn't work in your setup (would be weird
> though)?
> 
> [ ID][Role] Interval           Transfer     Bitrate         Retr
> [  5][TX-C]   0.00-10.01  sec  1.09 GBytes   935 Mbits/sec    0             sender
> [  5][TX-C]   0.00-10.01  sec  1.09 GBytes   932 Mbits/sec                  receiver
> [  7][RX-C]   0.00-10.01  sec  1.09 GBytes   933 Mbits/sec  154             sender
> [  7][RX-C]   0.00-10.01  sec  1.08 GBytes   931 Mbits/sec                  receiver

I suspect it's due to me hair pining mv88q2110 together on the same SoC.  
Unfortunately that is the only test setup I have for this device.

-- 
Kind Regards,
Niklas Söderlund

  reply	other threads:[~2024-10-05 11:08 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-06 13:39 [net-next 0/3] net: phy: marvell-88q2xxx: Enable auto negotiation for mv88q2110 Niklas Söderlund
2024-09-06 13:39 ` [net-next 1/3] net: phy: marvell-88q2xxx: Align soft reset for mv88q2110 and mv88q2220 Niklas Söderlund
2024-09-10 20:21   ` Andrew Lunn
2024-09-12 16:51   ` Dimitri Fedrau
2024-09-25 12:22   ` Stefan Eichenberger
2024-09-06 13:39 ` [net-next 2/3] net: phy: marvell-88q2xxx: Make register writer function generic Niklas Söderlund
2024-09-06 20:18   ` Andrew Lunn
2024-09-10 20:21   ` Andrew Lunn
2024-09-12 16:52   ` Dimitri Fedrau
2024-09-25 12:23   ` Stefan Eichenberger
2024-09-06 13:39 ` [net-next 3/3] net: phy: marvell-88q2xxx: Enable auto negotiation for mv88q2110 Niklas Söderlund
2024-09-06 20:36   ` Andrew Lunn
2024-09-06 21:39     ` Niklas Söderlund
2024-09-10 16:32       ` Andrew Lunn
2024-09-10 18:02         ` Stefan Eichenberger
2024-09-10 20:18           ` Andrew Lunn
2024-09-10 20:23   ` Andrew Lunn
2024-09-14 14:00     ` Stefan Eichenberger
2024-09-14 14:21       ` Niklas Söderlund
2024-09-14 14:43         ` Andrew Lunn
2024-09-25 13:04         ` Stefan Eichenberger
2024-10-05 11:08           ` Niklas Söderlund [this message]
2024-09-14 14:50       ` Andrew Lunn
2024-09-25 11:56         ` Stefan Eichenberger

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