From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com,
Oleksandr Kolomeiets <okl-plv@napatech.com>
Subject: [PATCH v1 11/50] net/ntnic: add categorizer (CAT) flow module
Date: Sun, 6 Oct 2024 22:36:38 +0200 [thread overview]
Message-ID: <20241006203728.330792-12-sil-plv@napatech.com> (raw)
In-Reply-To: <20241006203728.330792-1-sil-plv@napatech.com>
From: Oleksandr Kolomeiets <okl-plv@napatech.com>
The Categorizer module’s main purpose is to select the behavior
of other modules in the FPGA pipeline, depending on a protocol check.
Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
drivers/net/ntnic/include/hw_mod_backend.h | 51 +
drivers/net/ntnic/include/hw_mod_cat_v18.h | 141 +++
drivers/net/ntnic/include/hw_mod_cat_v21.h | 91 ++
drivers/net/ntnic/meson.build | 1 +
.../nthw/flow_api/flow_backend/flow_backend.c | 465 ++++++++++
.../ntnic/nthw/flow_filter/flow_nthw_cat.c | 872 ++++++++++++++++++
.../ntnic/nthw/flow_filter/flow_nthw_cat.h | 291 ++++++
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 +
.../nthw/supported/nthw_fpga_reg_defs_cat.h | 238 +++++
10 files changed, 2152 insertions(+)
create mode 100644 drivers/net/ntnic/include/hw_mod_cat_v18.h
create mode 100644 drivers/net/ntnic/include/hw_mod_cat_v21.h
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.c
create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h
index 11a0d62c41..ce2c0cf7cf 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -6,8 +6,40 @@
#ifndef _HW_MOD_BACKEND_H_
#define _HW_MOD_BACKEND_H_
+#include <stdbool.h>
+
+#include "hw_mod_cat_v18.h"
+#include "hw_mod_cat_v21.h"
+
#define MAX_PHYS_ADAPTERS 8
+#define COMMON_FUNC_INFO_S \
+ int ver; \
+ void *base; \
+ unsigned int alloced_size; \
+ int debug
+
+struct cat_func_s {
+ COMMON_FUNC_INFO_S;
+ uint32_t nb_cat_funcs;
+ uint32_t nb_flow_types;
+ uint32_t nb_pm_ext;
+ uint32_t nb_len;
+ uint32_t kcc_size;
+ uint32_t cts_num;
+ uint32_t kcc_banks;
+ uint32_t kcc_id_bit_size;
+ uint32_t kcc_records;
+ uint32_t km_if_count;
+ int32_t km_if_m0;
+ int32_t km_if_m1;
+
+ union {
+ struct hw_mod_cat_v18_s v18;
+ struct hw_mod_cat_v21_s v21;
+ };
+};
+
enum debug_mode_e {
FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000,
FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001
@@ -61,6 +93,25 @@ struct flow_api_backend_ops {
int (*alloc_rx_queue)(void *dev, int queue_id);
int (*free_rx_queue)(void *dev, int hw_queue);
+
+ /* CAT */
+ bool (*get_cat_present)(void *dev);
+ uint32_t (*get_cat_version)(void *dev);
+ int (*cat_cfn_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt);
+ int (*cat_kce_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int index,
+ int cnt);
+ int (*cat_kcs_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int cat_func,
+ int cnt);
+ int (*cat_fte_flush)(void *dev, const struct cat_func_s *cat, int km_if_idx, int index,
+ int cnt);
+ int (*cat_cte_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt);
+ int (*cat_cts_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt);
+ int (*cat_cot_flush)(void *dev, const struct cat_func_s *cat, int cat_func, int cnt);
+ int (*cat_cct_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt);
+ int (*cat_exo_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt);
+ int (*cat_rck_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt);
+ int (*cat_len_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt);
+ int (*cat_kcc_flush)(void *dev, const struct cat_func_s *cat, int index, int cnt);
};
struct flow_api_backend_s {
diff --git a/drivers/net/ntnic/include/hw_mod_cat_v18.h b/drivers/net/ntnic/include/hw_mod_cat_v18.h
new file mode 100644
index 0000000000..7ba38207a0
--- /dev/null
+++ b/drivers/net/ntnic/include/hw_mod_cat_v18.h
@@ -0,0 +1,141 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _HW_MOD_CAT_V18_H_
+#define _HW_MOD_CAT_V18_H_
+
+#include <stdint.h>
+
+struct cat_v18_cfn_s {
+ uint32_t enable;
+ uint32_t inv;
+ /* protocol checks */
+ uint32_t ptc_inv;
+ uint32_t ptc_isl;
+ uint32_t ptc_cfp;
+ uint32_t ptc_mac;
+ uint32_t ptc_l2;
+ uint32_t ptc_vntag;
+ uint32_t ptc_vlan;
+ uint32_t ptc_mpls;
+ uint32_t ptc_l3;
+ uint32_t ptc_frag;
+ uint32_t ptc_ip_prot;
+ uint32_t ptc_l4;
+ uint32_t ptc_tunnel;
+ uint32_t ptc_tnl_l2;
+ uint32_t ptc_tnl_vlan;
+ uint32_t ptc_tnl_mpls;
+ uint32_t ptc_tnl_l3;
+ uint32_t ptc_tnl_frag;
+ uint32_t ptc_tnl_ip_prot;
+ uint32_t ptc_tnl_l4;
+ /* error checks */
+ uint32_t err_inv;
+ uint32_t err_cv;
+ uint32_t err_fcs;
+ uint32_t err_trunc;
+ uint32_t err_l3_cs;
+ uint32_t err_l4_cs;
+ /* in port */
+ uint32_t mac_port;
+ /* pattern matcher */
+ uint32_t pm_cmp[2];
+ uint32_t pm_dct;
+ uint32_t pm_ext_inv;
+ uint32_t pm_cmb;
+ uint32_t pm_and_inv;
+ uint32_t pm_or_inv;
+ uint32_t pm_inv;
+ uint32_t lc;
+ uint32_t lc_inv;
+ uint32_t km_or;
+};
+
+struct cat_v18_kce_s {
+ uint32_t enable_bm;
+};
+
+struct cat_v18_kcs_s {
+ uint32_t category;
+};
+
+struct cat_v18_fte_s {
+ uint32_t enable_bm;
+};
+
+struct cat_v18_cte_s {
+ union {
+ uint32_t enable_bm;
+ struct {
+ uint32_t col : 1;
+ uint32_t cor : 1;
+ uint32_t hsh : 1;
+ uint32_t qsl : 1;
+ uint32_t ipf : 1;
+ uint32_t slc : 1;
+ uint32_t pdb : 1;
+ uint32_t msk : 1;
+ uint32_t hst : 1;
+ uint32_t epp : 1;
+ uint32_t tpe : 1;
+ } b;
+ };
+};
+
+struct cat_v18_cts_s {
+ uint32_t cat_a;
+ uint32_t cat_b;
+};
+
+struct cat_v18_cot_s {
+ uint32_t color;
+ uint32_t km;
+};
+
+struct cat_v18_cct_s {
+ uint32_t color;
+ uint32_t km;
+};
+
+struct cat_v18_exo_s {
+ uint32_t dyn;
+ int32_t ofs;
+};
+
+struct cat_v18_rck_s {
+ uint32_t rck_data;
+};
+
+struct cat_v18_len_s {
+ uint32_t lower;
+ uint32_t upper;
+ uint32_t dyn1;
+ uint32_t dyn2;
+ uint32_t inv;
+};
+
+struct cat_v18_kcc_s {
+ uint32_t key[2];
+ uint32_t category;
+ uint32_t id;
+};
+
+struct hw_mod_cat_v18_s {
+ struct cat_v18_cfn_s *cfn;
+ struct cat_v18_kce_s *kce;
+ struct cat_v18_kcs_s *kcs;
+ struct cat_v18_fte_s *fte;
+ struct cat_v18_cte_s *cte;
+ struct cat_v18_cts_s *cts;
+ struct cat_v18_cot_s *cot;
+ struct cat_v18_cct_s *cct;
+ struct cat_v18_exo_s *exo;
+ struct cat_v18_rck_s *rck;
+ struct cat_v18_len_s *len;
+ struct cat_v18_kcc_s *kcc_cam;
+};
+
+#endif /* _HW_MOD_CAT_V18_H_ */
diff --git a/drivers/net/ntnic/include/hw_mod_cat_v21.h b/drivers/net/ntnic/include/hw_mod_cat_v21.h
new file mode 100644
index 0000000000..7dd0038cf1
--- /dev/null
+++ b/drivers/net/ntnic/include/hw_mod_cat_v21.h
@@ -0,0 +1,91 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _HW_MOD_CAT_V21_H_
+#define _HW_MOD_CAT_V21_H_
+
+#include <stdint.h>
+
+#include "hw_mod_cat_v18.h"
+
+struct cat_v21_cfn_s {
+ uint32_t enable;
+ uint32_t inv;
+ /* protocol checks */
+ uint32_t ptc_inv;
+ uint32_t ptc_isl;
+ uint32_t ptc_cfp;
+ uint32_t ptc_mac;
+ uint32_t ptc_l2;
+ uint32_t ptc_vntag;
+ uint32_t ptc_vlan;
+ uint32_t ptc_mpls;
+ uint32_t ptc_l3;
+ uint32_t ptc_frag;
+ uint32_t ptc_ip_prot;
+ uint32_t ptc_l4;
+ uint32_t ptc_tunnel;
+ uint32_t ptc_tnl_l2;
+ uint32_t ptc_tnl_vlan;
+ uint32_t ptc_tnl_mpls;
+ uint32_t ptc_tnl_l3;
+ uint32_t ptc_tnl_frag;
+ uint32_t ptc_tnl_ip_prot;
+ uint32_t ptc_tnl_l4;
+ /* error checks */
+ uint32_t err_inv;
+ uint32_t err_cv;
+ uint32_t err_fcs;
+ uint32_t err_trunc;
+ uint32_t err_l3_cs;
+ uint32_t err_l4_cs;
+ uint32_t err_tnl_l3_cs;
+ uint32_t err_tnl_l4_cs;
+ uint32_t err_ttl_exp;
+ uint32_t err_tnl_ttl_exp;
+ /* in port */
+ uint32_t mac_port;
+ /* pattern matcher */
+ uint32_t pm_cmp[2];
+ uint32_t pm_dct;
+ uint32_t pm_ext_inv;
+ uint32_t pm_cmb;
+ uint32_t pm_and_inv;
+ uint32_t pm_or_inv;
+ uint32_t pm_inv;
+ uint32_t lc;
+ uint32_t lc_inv;
+ uint32_t km0_or;
+ uint32_t km1_or;
+};
+
+struct cat_v21_kce_s {
+ uint32_t enable_bm[2];
+};
+
+struct cat_v21_kcs_s {
+ uint32_t category[2];
+};
+
+struct cat_v21_fte_s {
+ uint32_t enable_bm[2];
+};
+
+struct hw_mod_cat_v21_s {
+ struct cat_v21_cfn_s *cfn;
+ struct cat_v21_kce_s *kce;
+ struct cat_v21_kcs_s *kcs;
+ struct cat_v21_fte_s *fte;
+ struct cat_v18_cte_s *cte;
+ struct cat_v18_cts_s *cts;
+ struct cat_v18_cot_s *cot;
+ struct cat_v18_cct_s *cct;
+ struct cat_v18_exo_s *exo;
+ struct cat_v18_rck_s *rck;
+ struct cat_v18_len_s *len;
+ struct cat_v18_kcc_s *kcc_cam;
+};
+
+#endif /* _HW_MOD_CAT_V21_H_ */
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index b771a600e4..09631fb84b 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -46,6 +46,7 @@ sources = files(
'nthw/flow_api/flow_api.c',
'nthw/flow_api/flow_backend/flow_backend.c',
'nthw/flow_api/flow_filter.c',
+ 'nthw/flow_filter/flow_nthw_cat.c',
'nthw/flow_filter/flow_nthw_info.c',
'nthw/model/nthw_fpga_model.c',
'nthw/nthw_platform.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
index f3ad3686d4..16cc24ec72 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
@@ -6,6 +6,7 @@
#include <stdint.h>
#include "flow_nthw_info.h"
+#include "flow_nthw_cat.h"
#include "ntnic_mod_reg.h"
#include "nthw_fpga_model.h"
#include "hw_mod_backend.h"
@@ -21,8 +22,23 @@ static struct backend_dev_s {
uint8_t adapter_no;
enum debug_mode_e dmode;
struct info_nthw *p_info_nthw;
+ struct cat_nthw *p_cat_nthw;
} be_devs[MAX_PHYS_ADAPTERS];
+#define CHECK_DEBUG_ON(be, mod, inst) \
+ int __debug__ = 0; \
+ if (((be)->dmode & FLOW_BACKEND_DEBUG_MODE_WRITE) || (mod)->debug) \
+ do { \
+ mod##_nthw_set_debug_mode((inst), 0xFF); \
+ __debug__ = 1; \
+ } while (0)
+
+#define CHECK_DEBUG_OFF(mod, inst) \
+ do { \
+ if (__debug__) \
+ mod##_nthw_set_debug_mode((inst), 0); \
+ } while (0)
+
const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, void **be_dev);
static void bin_flow_backend_done(void *be_dev);
@@ -283,6 +299,427 @@ static int get_nb_hsh_toeplitz(void *be_dev)
return info_nthw_get_nb_hsh_toeplitz(be->p_info_nthw);
}
+/*
+ * CAT
+ */
+
+static bool cat_get_present(void *be_dev)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ return be->p_cat_nthw != NULL;
+}
+
+static uint32_t cat_get_version(void *be_dev)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ return (uint32_t)((nthw_module_get_major_version(be->p_cat_nthw->m_cat) << 16) |
+ (nthw_module_get_minor_version(be->p_cat_nthw->m_cat) & 0xffff));
+}
+
+static int cat_cfn_flush(void *be_dev, const struct cat_func_s *cat, int cat_func, int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18) {
+ cat_nthw_cfn_cnt(be->p_cat_nthw, 1U);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_cfn_select(be->p_cat_nthw, cat_func);
+ cat_nthw_cfn_enable(be->p_cat_nthw, cat->v18.cfn[cat_func].enable);
+ cat_nthw_cfn_inv(be->p_cat_nthw, cat->v18.cfn[cat_func].inv);
+ cat_nthw_cfn_ptc_inv(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_inv);
+ cat_nthw_cfn_ptc_isl(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_isl);
+ cat_nthw_cfn_ptc_cfp(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_cfp);
+ cat_nthw_cfn_ptc_mac(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_mac);
+ cat_nthw_cfn_ptc_l2(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_l2);
+ cat_nthw_cfn_ptc_vn_tag(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_vntag);
+ cat_nthw_cfn_ptc_vlan(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_vlan);
+ cat_nthw_cfn_ptc_mpls(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_mpls);
+ cat_nthw_cfn_ptc_l3(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_l3);
+ cat_nthw_cfn_ptc_frag(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_frag);
+ cat_nthw_cfn_ptc_ip_prot(be->p_cat_nthw,
+ cat->v18.cfn[cat_func].ptc_ip_prot);
+ cat_nthw_cfn_ptc_l4(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_l4);
+ cat_nthw_cfn_ptc_tunnel(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_tunnel);
+ cat_nthw_cfn_ptc_tnl_l2(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_tnl_l2);
+ cat_nthw_cfn_ptc_tnl_vlan(be->p_cat_nthw,
+ cat->v18.cfn[cat_func].ptc_tnl_vlan);
+ cat_nthw_cfn_ptc_tnl_mpls(be->p_cat_nthw,
+ cat->v18.cfn[cat_func].ptc_tnl_mpls);
+ cat_nthw_cfn_ptc_tnl_l3(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_tnl_l3);
+ cat_nthw_cfn_ptc_tnl_frag(be->p_cat_nthw,
+ cat->v18.cfn[cat_func].ptc_tnl_frag);
+ cat_nthw_cfn_ptc_tnl_ip_prot(be->p_cat_nthw,
+ cat->v18.cfn[cat_func].ptc_tnl_ip_prot);
+ cat_nthw_cfn_ptc_tnl_l4(be->p_cat_nthw, cat->v18.cfn[cat_func].ptc_tnl_l4);
+
+ cat_nthw_cfn_err_inv(be->p_cat_nthw, cat->v18.cfn[cat_func].err_inv);
+ cat_nthw_cfn_err_cv(be->p_cat_nthw, cat->v18.cfn[cat_func].err_cv);
+ cat_nthw_cfn_err_fcs(be->p_cat_nthw, cat->v18.cfn[cat_func].err_fcs);
+ cat_nthw_cfn_err_trunc(be->p_cat_nthw, cat->v18.cfn[cat_func].err_trunc);
+ cat_nthw_cfn_err_l3_cs(be->p_cat_nthw, cat->v18.cfn[cat_func].err_l3_cs);
+ cat_nthw_cfn_err_l4_cs(be->p_cat_nthw, cat->v18.cfn[cat_func].err_l4_cs);
+
+ cat_nthw_cfn_mac_port(be->p_cat_nthw, cat->v18.cfn[cat_func].mac_port);
+
+ cat_nthw_cfn_pm_cmp(be->p_cat_nthw, cat->v18.cfn[cat_func].pm_cmp);
+ cat_nthw_cfn_pm_dct(be->p_cat_nthw, cat->v18.cfn[cat_func].pm_dct);
+ cat_nthw_cfn_pm_ext_inv(be->p_cat_nthw, cat->v18.cfn[cat_func].pm_ext_inv);
+ cat_nthw_cfn_pm_cmb(be->p_cat_nthw, cat->v18.cfn[cat_func].pm_cmb);
+ cat_nthw_cfn_pm_and_inv(be->p_cat_nthw, cat->v18.cfn[cat_func].pm_and_inv);
+ cat_nthw_cfn_pm_or_inv(be->p_cat_nthw, cat->v18.cfn[cat_func].pm_or_inv);
+ cat_nthw_cfn_pm_inv(be->p_cat_nthw, cat->v18.cfn[cat_func].pm_inv);
+
+ cat_nthw_cfn_lc(be->p_cat_nthw, cat->v18.cfn[cat_func].lc);
+ cat_nthw_cfn_lc_inv(be->p_cat_nthw, cat->v18.cfn[cat_func].lc_inv);
+ cat_nthw_cfn_km0_or(be->p_cat_nthw, cat->v18.cfn[cat_func].km_or);
+ cat_nthw_cfn_flush(be->p_cat_nthw);
+ cat_func++;
+ }
+
+ } else if (cat->ver == 21) {
+ cat_nthw_cfn_cnt(be->p_cat_nthw, 1U);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_cfn_select(be->p_cat_nthw, cat_func);
+ cat_nthw_cfn_enable(be->p_cat_nthw, cat->v21.cfn[cat_func].enable);
+ cat_nthw_cfn_inv(be->p_cat_nthw, cat->v21.cfn[cat_func].inv);
+ cat_nthw_cfn_ptc_inv(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_inv);
+ cat_nthw_cfn_ptc_isl(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_isl);
+ cat_nthw_cfn_ptc_cfp(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_cfp);
+ cat_nthw_cfn_ptc_mac(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_mac);
+ cat_nthw_cfn_ptc_l2(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_l2);
+ cat_nthw_cfn_ptc_vn_tag(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_vntag);
+ cat_nthw_cfn_ptc_vlan(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_vlan);
+ cat_nthw_cfn_ptc_mpls(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_mpls);
+ cat_nthw_cfn_ptc_l3(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_l3);
+ cat_nthw_cfn_ptc_frag(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_frag);
+ cat_nthw_cfn_ptc_ip_prot(be->p_cat_nthw,
+ cat->v21.cfn[cat_func].ptc_ip_prot);
+ cat_nthw_cfn_ptc_l4(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_l4);
+ cat_nthw_cfn_ptc_tunnel(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_tunnel);
+ cat_nthw_cfn_ptc_tnl_l2(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_tnl_l2);
+ cat_nthw_cfn_ptc_tnl_vlan(be->p_cat_nthw,
+ cat->v21.cfn[cat_func].ptc_tnl_vlan);
+ cat_nthw_cfn_ptc_tnl_mpls(be->p_cat_nthw,
+ cat->v21.cfn[cat_func].ptc_tnl_mpls);
+ cat_nthw_cfn_ptc_tnl_l3(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_tnl_l3);
+ cat_nthw_cfn_ptc_tnl_frag(be->p_cat_nthw,
+ cat->v21.cfn[cat_func].ptc_tnl_frag);
+ cat_nthw_cfn_ptc_tnl_ip_prot(be->p_cat_nthw,
+ cat->v21.cfn[cat_func].ptc_tnl_ip_prot);
+ cat_nthw_cfn_ptc_tnl_l4(be->p_cat_nthw, cat->v21.cfn[cat_func].ptc_tnl_l4);
+
+ cat_nthw_cfn_err_inv(be->p_cat_nthw, cat->v21.cfn[cat_func].err_inv);
+ cat_nthw_cfn_err_cv(be->p_cat_nthw, cat->v21.cfn[cat_func].err_cv);
+ cat_nthw_cfn_err_fcs(be->p_cat_nthw, cat->v21.cfn[cat_func].err_fcs);
+ cat_nthw_cfn_err_trunc(be->p_cat_nthw, cat->v21.cfn[cat_func].err_trunc);
+ cat_nthw_cfn_err_l3_cs(be->p_cat_nthw, cat->v21.cfn[cat_func].err_l3_cs);
+ cat_nthw_cfn_err_l4_cs(be->p_cat_nthw, cat->v21.cfn[cat_func].err_l4_cs);
+ cat_nthw_cfn_err_tnl_l3_cs(be->p_cat_nthw,
+ cat->v21.cfn[cat_func].err_tnl_l3_cs);
+ cat_nthw_cfn_err_tnl_l4_cs(be->p_cat_nthw,
+ cat->v21.cfn[cat_func].err_tnl_l4_cs);
+ cat_nthw_cfn_err_ttl_exp(be->p_cat_nthw,
+ cat->v21.cfn[cat_func].err_ttl_exp);
+ cat_nthw_cfn_err_tnl_ttl_exp(be->p_cat_nthw,
+ cat->v21.cfn[cat_func].err_tnl_ttl_exp);
+
+ cat_nthw_cfn_mac_port(be->p_cat_nthw, cat->v21.cfn[cat_func].mac_port);
+
+ cat_nthw_cfn_pm_cmp(be->p_cat_nthw, cat->v21.cfn[cat_func].pm_cmp);
+ cat_nthw_cfn_pm_dct(be->p_cat_nthw, cat->v21.cfn[cat_func].pm_dct);
+ cat_nthw_cfn_pm_ext_inv(be->p_cat_nthw, cat->v21.cfn[cat_func].pm_ext_inv);
+ cat_nthw_cfn_pm_cmb(be->p_cat_nthw, cat->v21.cfn[cat_func].pm_cmb);
+ cat_nthw_cfn_pm_and_inv(be->p_cat_nthw, cat->v21.cfn[cat_func].pm_and_inv);
+ cat_nthw_cfn_pm_or_inv(be->p_cat_nthw, cat->v21.cfn[cat_func].pm_or_inv);
+ cat_nthw_cfn_pm_inv(be->p_cat_nthw, cat->v21.cfn[cat_func].pm_inv);
+
+ cat_nthw_cfn_lc(be->p_cat_nthw, cat->v21.cfn[cat_func].lc);
+ cat_nthw_cfn_lc_inv(be->p_cat_nthw, cat->v21.cfn[cat_func].lc_inv);
+ cat_nthw_cfn_km0_or(be->p_cat_nthw, cat->v21.cfn[cat_func].km0_or);
+
+ if (be->p_cat_nthw->m_km_if_cnt > 1)
+ cat_nthw_cfn_km1_or(be->p_cat_nthw, cat->v21.cfn[cat_func].km1_or);
+
+ cat_nthw_cfn_flush(be->p_cat_nthw);
+ cat_func++;
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_kce_flush(void *be_dev, const struct cat_func_s *cat, int km_if_idx, int index,
+ int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18) {
+ cat_nthw_kce_cnt(be->p_cat_nthw, 0, 1U);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_kce_select(be->p_cat_nthw, 0, index + i);
+ cat_nthw_kce_enable(be->p_cat_nthw, 0, cat->v18.kce[index + i].enable_bm);
+ cat_nthw_kce_flush(be->p_cat_nthw, 0);
+ }
+
+ } else if (cat->ver == 21) {
+ cat_nthw_kce_cnt(be->p_cat_nthw, km_if_idx, 1U);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_kce_select(be->p_cat_nthw, km_if_idx, index + i);
+ cat_nthw_kce_enable(be->p_cat_nthw, km_if_idx,
+ cat->v21.kce[index + i].enable_bm[km_if_idx]);
+ cat_nthw_kce_flush(be->p_cat_nthw, km_if_idx);
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_kcs_flush(void *be_dev, const struct cat_func_s *cat, int km_if_idx, int cat_func,
+ int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18) {
+ cat_nthw_kcs_cnt(be->p_cat_nthw, 0, 1U);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_kcs_select(be->p_cat_nthw, 0, cat_func);
+ cat_nthw_kcs_category(be->p_cat_nthw, 0, cat->v18.kcs[cat_func].category);
+ cat_nthw_kcs_flush(be->p_cat_nthw, 0);
+ cat_func++;
+ }
+
+ } else if (cat->ver == 21) {
+ cat_nthw_kcs_cnt(be->p_cat_nthw, km_if_idx, 1U);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_kcs_select(be->p_cat_nthw, km_if_idx, cat_func);
+ cat_nthw_kcs_category(be->p_cat_nthw, km_if_idx,
+ cat->v21.kcs[cat_func].category[km_if_idx]);
+ cat_nthw_kcs_flush(be->p_cat_nthw, km_if_idx);
+ cat_func++;
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_fte_flush(void *be_dev, const struct cat_func_s *cat, int km_if_idx, int index,
+ int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18) {
+ cat_nthw_fte_cnt(be->p_cat_nthw, 0, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_fte_select(be->p_cat_nthw, 0, index + i);
+ cat_nthw_fte_enable(be->p_cat_nthw, 0, cat->v18.fte[index + i].enable_bm);
+ cat_nthw_fte_flush(be->p_cat_nthw, 0);
+ }
+
+ } else if (cat->ver == 21) {
+ cat_nthw_fte_cnt(be->p_cat_nthw, km_if_idx, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_fte_select(be->p_cat_nthw, km_if_idx, index + i);
+ cat_nthw_fte_enable(be->p_cat_nthw, km_if_idx,
+ cat->v21.fte[index + i].enable_bm[km_if_idx]);
+ cat_nthw_fte_flush(be->p_cat_nthw, km_if_idx);
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_cte_flush(void *be_dev, const struct cat_func_s *cat, int cat_func, int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18 || cat->ver == 21) {
+ cat_nthw_cte_cnt(be->p_cat_nthw, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_cte_select(be->p_cat_nthw, cat_func);
+ cat_nthw_cte_enable_col(be->p_cat_nthw, cat->v18.cte[cat_func].b.col);
+ cat_nthw_cte_enable_cor(be->p_cat_nthw, cat->v18.cte[cat_func].b.cor);
+ cat_nthw_cte_enable_hsh(be->p_cat_nthw, cat->v18.cte[cat_func].b.hsh);
+ cat_nthw_cte_enable_qsl(be->p_cat_nthw, cat->v18.cte[cat_func].b.qsl);
+ cat_nthw_cte_enable_ipf(be->p_cat_nthw, cat->v18.cte[cat_func].b.ipf);
+ cat_nthw_cte_enable_slc(be->p_cat_nthw, cat->v18.cte[cat_func].b.slc);
+ cat_nthw_cte_enable_pdb(be->p_cat_nthw, cat->v18.cte[cat_func].b.pdb);
+ cat_nthw_cte_enable_msk(be->p_cat_nthw, cat->v18.cte[cat_func].b.msk);
+ cat_nthw_cte_enable_hst(be->p_cat_nthw, cat->v18.cte[cat_func].b.hst);
+ cat_nthw_cte_enable_epp(be->p_cat_nthw, cat->v18.cte[cat_func].b.epp);
+ cat_nthw_cte_enable_tpe(be->p_cat_nthw, cat->v18.cte[cat_func].b.tpe);
+
+ cat_nthw_cte_flush(be->p_cat_nthw);
+ cat_func++;
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_cts_flush(void *be_dev, const struct cat_func_s *cat, int index, int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18 || cat->ver == 21) {
+ cat_nthw_cts_cnt(be->p_cat_nthw, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_cts_select(be->p_cat_nthw, index + i);
+ cat_nthw_cts_cat_a(be->p_cat_nthw, cat->v18.cts[index + i].cat_a);
+ cat_nthw_cts_cat_b(be->p_cat_nthw, cat->v18.cts[index + i].cat_b);
+ cat_nthw_cts_flush(be->p_cat_nthw);
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_cot_flush(void *be_dev, const struct cat_func_s *cat, int cat_func, int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18 || cat->ver == 21) {
+ cat_nthw_cot_cnt(be->p_cat_nthw, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_cot_select(be->p_cat_nthw, cat_func + i);
+ cat_nthw_cot_color(be->p_cat_nthw, cat->v18.cot[cat_func + i].color);
+ cat_nthw_cot_km(be->p_cat_nthw, cat->v18.cot[cat_func + i].km);
+ cat_nthw_cot_flush(be->p_cat_nthw);
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_cct_flush(void *be_dev, const struct cat_func_s *cat, int index, int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18 || cat->ver == 21) {
+ cat_nthw_cct_cnt(be->p_cat_nthw, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_cct_select(be->p_cat_nthw, index + i);
+ cat_nthw_cct_color(be->p_cat_nthw, cat->v18.cct[index + i].color);
+ cat_nthw_cct_km(be->p_cat_nthw, cat->v18.cct[index + i].km);
+ cat_nthw_cct_flush(be->p_cat_nthw);
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_exo_flush(void *be_dev, const struct cat_func_s *cat, int ext_index, int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18 || cat->ver == 21) {
+ cat_nthw_exo_cnt(be->p_cat_nthw, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_exo_select(be->p_cat_nthw, ext_index + i);
+ cat_nthw_exo_dyn(be->p_cat_nthw, cat->v18.exo[ext_index + i].dyn);
+ cat_nthw_exo_ofs(be->p_cat_nthw, cat->v18.exo[ext_index + i].ofs);
+ cat_nthw_exo_flush(be->p_cat_nthw);
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_rck_flush(void *be_dev, const struct cat_func_s *cat, int index, int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18 || cat->ver == 21) {
+ cat_nthw_rck_cnt(be->p_cat_nthw, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_rck_select(be->p_cat_nthw, index + i);
+ cat_nthw_rck_data(be->p_cat_nthw, cat->v18.rck[index + i].rck_data);
+ cat_nthw_rck_flush(be->p_cat_nthw);
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_len_flush(void *be_dev, const struct cat_func_s *cat, int len_index, int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18 || cat->ver == 21) {
+ cat_nthw_len_cnt(be->p_cat_nthw, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_len_select(be->p_cat_nthw, len_index + i);
+ cat_nthw_len_lower(be->p_cat_nthw, cat->v18.len[len_index + i].lower);
+ cat_nthw_len_upper(be->p_cat_nthw, cat->v18.len[len_index + i].upper);
+ cat_nthw_len_dyn1(be->p_cat_nthw, cat->v18.len[len_index + i].dyn1);
+ cat_nthw_len_dyn2(be->p_cat_nthw, cat->v18.len[len_index + i].dyn2);
+ cat_nthw_len_inv(be->p_cat_nthw, cat->v18.len[len_index + i].inv);
+ cat_nthw_len_flush(be->p_cat_nthw);
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
+static int cat_kcc_flush(void *be_dev, const struct cat_func_s *cat, int len_index, int cnt)
+{
+ struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+ CHECK_DEBUG_ON(be, cat, be->p_cat_nthw);
+
+ if (cat->ver == 18 || cat->ver == 21) {
+ cat_nthw_kcc_cnt(be->p_cat_nthw, 1);
+
+ for (int i = 0; i < cnt; i++) {
+ cat_nthw_kcc_select(be->p_cat_nthw, len_index + i);
+ cat_nthw_kcc_key(be->p_cat_nthw, cat->v18.kcc_cam[len_index + i].key);
+ cat_nthw_kcc_category(be->p_cat_nthw,
+ cat->v18.kcc_cam[len_index + i].category);
+ cat_nthw_kcc_id(be->p_cat_nthw, cat->v18.kcc_cam[len_index + i].id);
+ cat_nthw_kcc_flush(be->p_cat_nthw);
+ }
+ }
+
+ CHECK_DEBUG_OFF(cat, be->p_cat_nthw);
+ return 0;
+}
+
/*
* DBS
*/
@@ -351,6 +788,23 @@ const struct flow_api_backend_ops flow_be_iface = {
alloc_rx_queue,
free_rx_queue,
+
+ cat_get_present,
+ cat_get_version,
+ cat_cfn_flush,
+
+ cat_kce_flush,
+ cat_kcs_flush,
+ cat_fte_flush,
+
+ cat_cte_flush,
+ cat_cts_flush,
+ cat_cot_flush,
+ cat_cct_flush,
+ cat_exo_flush,
+ cat_rck_flush,
+ cat_len_flush,
+ cat_kcc_flush,
};
const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, void **dev)
@@ -361,6 +815,16 @@ const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo
info_nthw_init(pinfonthw, p_fpga, physical_adapter_no);
be_devs[physical_adapter_no].p_info_nthw = pinfonthw;
+ /* Init nthw CAT */
+ if (cat_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) {
+ struct cat_nthw *pcatnthw = cat_nthw_new();
+ cat_nthw_init(pcatnthw, p_fpga, physical_adapter_no);
+ be_devs[physical_adapter_no].p_cat_nthw = pcatnthw;
+
+ } else {
+ be_devs[physical_adapter_no].p_cat_nthw = NULL;
+ }
+
be_devs[physical_adapter_no].adapter_no = physical_adapter_no;
*dev = (void *)&be_devs[physical_adapter_no];
@@ -371,6 +835,7 @@ static void bin_flow_backend_done(void *dev)
{
struct backend_dev_s *be_dev = (struct backend_dev_s *)dev;
info_nthw_delete(be_dev->p_info_nthw);
+ cat_nthw_delete(be_dev->p_cat_nthw);
}
static const struct flow_backend_ops ops = {
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.c
new file mode 100644
index 0000000000..7d4631f813
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.c
@@ -0,0 +1,872 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "flow_nthw_cat.h"
+
+struct cat_nthw *cat_nthw_new(void)
+{
+ struct cat_nthw *p = malloc(sizeof(struct cat_nthw));
+
+ if (p)
+ (void)memset(p, 0, sizeof(*p));
+
+ return p;
+}
+
+void cat_nthw_delete(struct cat_nthw *p)
+{
+ if (p) {
+ (void)memset(p, 0, sizeof(*p));
+ free(p);
+ }
+}
+
+void cat_nthw_set_debug_mode(struct cat_nthw *p, unsigned int n_debug_mode)
+{
+ nthw_module_set_debug_mode(p->m_cat, n_debug_mode);
+}
+
+int cat_nthw_init(struct cat_nthw *p, nthw_fpga_t *p_fpga, int n_instance)
+{
+ const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+ nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_CAT, n_instance);
+
+ assert(n_instance >= 0 && n_instance < 256);
+
+ if (p == NULL)
+ return p_mod == NULL ? -1 : 0;
+
+ if (p_mod == NULL) {
+ NT_LOG(ERR, NTHW, "%s: Cat %d: no such instance\n", p_adapter_id_str, n_instance);
+ return -1;
+ }
+
+ p->mp_fpga = p_fpga;
+ p->m_physical_adapter_no = (uint8_t)n_instance;
+ p->m_cat = p_mod;
+
+ p->m_km_if_cnt = nthw_fpga_get_product_param(p->mp_fpga, NT_CAT_KM_IF_CNT, -1);
+
+ /* CFN */
+ p->mp_cfn_ctrl = nthw_module_get_register(p->m_cat, CAT_CFN_CTRL);
+ p->mp_cfn_addr = nthw_register_get_field(p->mp_cfn_ctrl, CAT_CFN_CTRL_ADR);
+ p->mp_cfn_cnt = nthw_register_get_field(p->mp_cfn_ctrl, CAT_CFN_CTRL_CNT);
+ p->mp_cfn_data = nthw_module_get_register(p->m_cat, CAT_CFN_DATA);
+ p->mp_cfn_data_enable = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_ENABLE);
+ p->mp_cfn_data_inv = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_INV);
+ p->mp_cfn_data_ptc_inv = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_INV);
+ p->mp_cfn_data_ptc_isl = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_ISL);
+ p->mp_cfn_data_ptc_mac = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_MAC);
+ p->mp_cfn_data_ptc_l2 = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_L2);
+ p->mp_cfn_data_ptc_vn_tag =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_VNTAG);
+ p->mp_cfn_data_ptc_vlan = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_VLAN);
+ p->mp_cfn_data_ptc_mpls = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_MPLS);
+ p->mp_cfn_data_ptc_l3 = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_L3);
+ p->mp_cfn_data_ptc_frag = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_FRAG);
+ p->mp_cfn_data_ptc_ip_prot =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_IP_PROT);
+ p->mp_cfn_data_ptc_l4 = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_L4);
+ p->mp_cfn_data_ptc_tunnel =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_TUNNEL);
+ p->mp_cfn_data_ptc_tnl_l2 =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_TNL_L2);
+ p->mp_cfn_data_ptc_tnl_vlan =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_TNL_VLAN);
+ p->mp_cfn_data_ptc_tnl_mpls =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_TNL_MPLS);
+ p->mp_cfn_data_ptc_tnl_l3 =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_TNL_L3);
+ p->mp_cfn_data_ptc_tnl_frag =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_TNL_FRAG);
+ p->mp_cfn_data_ptc_tnl_ip_prot =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_TNL_IP_PROT);
+ p->mp_cfn_data_ptc_tnl_l4 =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_TNL_L4);
+ p->mp_cfn_data_err_inv = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_INV);
+ p->mp_cfn_data_err_cv = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_CV);
+ p->mp_cfn_data_err_fcs = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_FCS);
+ p->mp_cfn_data_err_trunc = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_TRUNC);
+ p->mp_cfn_data_mac_port = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_MAC_PORT);
+ p->mp_cfn_data_pm_cmp = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PM_CMP);
+ p->mp_cfn_data_pm_dct = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PM_DCT);
+ p->mp_cfn_data_pm_ext_inv =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PM_EXT_INV);
+ p->mp_cfn_data_pm_cmb = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PM_CMB);
+ p->mp_cfn_data_pm_and_inv =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PM_AND_INV);
+ p->mp_cfn_data_pm_or_inv = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PM_OR_INV);
+ p->mp_cfn_data_pm_inv = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_PM_INV);
+ p->mp_cfn_data_lc = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_LC);
+ p->mp_cfn_data_lc_inv = nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_LC_INV);
+
+ if (p->m_km_if_cnt == -1) {
+ p->mp_cfn_data_km0_or =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_KM_OR);
+
+ } else {
+ p->mp_cfn_data_km0_or =
+ nthw_register_get_field(p->mp_cfn_data, CAT_CFN_DATA_KM0_OR);
+ p->mp_cfn_data_km1_or =
+ nthw_register_query_field(p->mp_cfn_data, CAT_CFN_DATA_KM1_OR);
+ }
+
+ if (p->m_km_if_cnt < 0) {
+ /* KCE */
+ p->mp_kce_ctrl[0] = nthw_module_get_register(p->m_cat, CAT_KCE_CTRL);
+ p->mp_kce_addr[0] = nthw_register_get_field(p->mp_kce_ctrl[0], CAT_KCE_CTRL_ADR);
+ p->mp_kce_cnt[0] = nthw_register_get_field(p->mp_kce_ctrl[0], CAT_KCE_CTRL_CNT);
+ p->mp_kce_data[0] = nthw_module_get_register(p->m_cat, CAT_KCE_DATA);
+ p->mp_kce_data_enable[0] =
+ nthw_register_get_field(p->mp_kce_data[0], CAT_KCE_DATA_ENABLE);
+ /* KCS */
+ p->mp_kcs_ctrl[0] = nthw_module_get_register(p->m_cat, CAT_KCS_CTRL);
+ p->mp_kcs_addr[0] = nthw_register_get_field(p->mp_kcs_ctrl[0], CAT_KCS_CTRL_ADR);
+ p->mp_kcs_cnt[0] = nthw_register_get_field(p->mp_kcs_ctrl[0], CAT_KCS_CTRL_CNT);
+ p->mp_kcs_data[0] = nthw_module_get_register(p->m_cat, CAT_KCS_DATA);
+ p->mp_kcs_data_category[0] =
+ nthw_register_get_field(p->mp_kcs_data[0], CAT_KCS_DATA_CATEGORY);
+ /* FTE */
+ p->mp_fte_ctrl[0] = nthw_module_get_register(p->m_cat, CAT_FTE_CTRL);
+ p->mp_fte_addr[0] = nthw_register_get_field(p->mp_fte_ctrl[0], CAT_FTE_CTRL_ADR);
+ p->mp_fte_cnt[0] = nthw_register_get_field(p->mp_fte_ctrl[0], CAT_FTE_CTRL_CNT);
+ p->mp_fte_data[0] = nthw_module_get_register(p->m_cat, CAT_FTE_DATA);
+ p->mp_fte_data_enable[0] =
+ nthw_register_get_field(p->mp_fte_data[0], CAT_FTE_DATA_ENABLE);
+
+ } else {
+ /* KCE 0 */
+ p->mp_kce_ctrl[0] = nthw_module_get_register(p->m_cat, CAT_KCE0_CTRL);
+ p->mp_kce_addr[0] = nthw_register_get_field(p->mp_kce_ctrl[0], CAT_KCE0_CTRL_ADR);
+ p->mp_kce_cnt[0] = nthw_register_get_field(p->mp_kce_ctrl[0], CAT_KCE0_CTRL_CNT);
+ p->mp_kce_data[0] = nthw_module_get_register(p->m_cat, CAT_KCE0_DATA);
+ p->mp_kce_data_enable[0] =
+ nthw_register_get_field(p->mp_kce_data[0], CAT_KCE0_DATA_ENABLE);
+ /* KCS 0 */
+ p->mp_kcs_ctrl[0] = nthw_module_get_register(p->m_cat, CAT_KCS0_CTRL);
+ p->mp_kcs_addr[0] = nthw_register_get_field(p->mp_kcs_ctrl[0], CAT_KCS0_CTRL_ADR);
+ p->mp_kcs_cnt[0] = nthw_register_get_field(p->mp_kcs_ctrl[0], CAT_KCS0_CTRL_CNT);
+ p->mp_kcs_data[0] = nthw_module_get_register(p->m_cat, CAT_KCS0_DATA);
+ p->mp_kcs_data_category[0] =
+ nthw_register_get_field(p->mp_kcs_data[0], CAT_KCS0_DATA_CATEGORY);
+ /* FTE 0 */
+ p->mp_fte_ctrl[0] = nthw_module_get_register(p->m_cat, CAT_FTE0_CTRL);
+ p->mp_fte_addr[0] = nthw_register_get_field(p->mp_fte_ctrl[0], CAT_FTE0_CTRL_ADR);
+ p->mp_fte_cnt[0] = nthw_register_get_field(p->mp_fte_ctrl[0], CAT_FTE0_CTRL_CNT);
+ p->mp_fte_data[0] = nthw_module_get_register(p->m_cat, CAT_FTE0_DATA);
+ p->mp_fte_data_enable[0] =
+ nthw_register_get_field(p->mp_fte_data[0], CAT_FTE0_DATA_ENABLE);
+ /* KCE 1 */
+ p->mp_kce_ctrl[1] = nthw_module_get_register(p->m_cat, CAT_KCE1_CTRL);
+ p->mp_kce_addr[1] = nthw_register_get_field(p->mp_kce_ctrl[1], CAT_KCE1_CTRL_ADR);
+ p->mp_kce_cnt[1] = nthw_register_get_field(p->mp_kce_ctrl[1], CAT_KCE1_CTRL_CNT);
+ p->mp_kce_data[1] = nthw_module_get_register(p->m_cat, CAT_KCE1_DATA);
+ p->mp_kce_data_enable[1] =
+ nthw_register_get_field(p->mp_kce_data[1], CAT_KCE1_DATA_ENABLE);
+ /* KCS 1 */
+ p->mp_kcs_ctrl[1] = nthw_module_get_register(p->m_cat, CAT_KCS1_CTRL);
+ p->mp_kcs_addr[1] = nthw_register_get_field(p->mp_kcs_ctrl[1], CAT_KCS1_CTRL_ADR);
+ p->mp_kcs_cnt[1] = nthw_register_get_field(p->mp_kcs_ctrl[1], CAT_KCS1_CTRL_CNT);
+ p->mp_kcs_data[1] = nthw_module_get_register(p->m_cat, CAT_KCS1_DATA);
+ p->mp_kcs_data_category[1] =
+ nthw_register_get_field(p->mp_kcs_data[1], CAT_KCS1_DATA_CATEGORY);
+ /* FTE 1 */
+ p->mp_fte_ctrl[1] = nthw_module_get_register(p->m_cat, CAT_FTE1_CTRL);
+ p->mp_fte_addr[1] = nthw_register_get_field(p->mp_fte_ctrl[1], CAT_FTE1_CTRL_ADR);
+ p->mp_fte_cnt[1] = nthw_register_get_field(p->mp_fte_ctrl[1], CAT_FTE1_CTRL_CNT);
+ p->mp_fte_data[1] = nthw_module_get_register(p->m_cat, CAT_FTE1_DATA);
+ p->mp_fte_data_enable[1] =
+ nthw_register_get_field(p->mp_fte_data[1], CAT_FTE1_DATA_ENABLE);
+ }
+
+ /* CTE */
+ p->mp_cte_ctrl = nthw_module_get_register(p->m_cat, CAT_CTE_CTRL);
+ p->mp_cte_addr = nthw_register_get_field(p->mp_cte_ctrl, CAT_CTE_CTRL_ADR);
+ p->mp_cte_cnt = nthw_register_get_field(p->mp_cte_ctrl, CAT_CTE_CTRL_CNT);
+ p->mp_cte_data = nthw_module_get_register(p->m_cat, CAT_CTE_DATA);
+ p->mp_cte_data_col = nthw_register_get_field(p->mp_cte_data, CAT_CTE_DATA_COL_ENABLE);
+ p->mp_cte_data_cor = nthw_register_get_field(p->mp_cte_data, CAT_CTE_DATA_COR_ENABLE);
+ p->mp_cte_data_hsh = nthw_register_get_field(p->mp_cte_data, CAT_CTE_DATA_HSH_ENABLE);
+ p->mp_cte_data_qsl = nthw_register_get_field(p->mp_cte_data, CAT_CTE_DATA_QSL_ENABLE);
+ p->mp_cte_data_ipf = nthw_register_get_field(p->mp_cte_data, CAT_CTE_DATA_IPF_ENABLE);
+ p->mp_cte_data_slc = nthw_register_get_field(p->mp_cte_data, CAT_CTE_DATA_SLC_ENABLE);
+ p->mp_cte_data_pdb = nthw_register_get_field(p->mp_cte_data, CAT_CTE_DATA_PDB_ENABLE);
+ p->mp_cte_data_msk = nthw_register_query_field(p->mp_cte_data, CAT_CTE_DATA_MSK_ENABLE);
+ p->mp_cte_data_hst = nthw_register_query_field(p->mp_cte_data, CAT_CTE_DATA_HST_ENABLE);
+ p->mp_cte_data_epp = nthw_register_query_field(p->mp_cte_data, CAT_CTE_DATA_EPP_ENABLE);
+ p->mp_cte_data_tpe = nthw_register_query_field(p->mp_cte_data, CAT_CTE_DATA_TPE_ENABLE);
+ /* CTS */
+ p->mp_cts_ctrl = nthw_module_get_register(p->m_cat, CAT_CTS_CTRL);
+ p->mp_cts_addr = nthw_register_get_field(p->mp_cts_ctrl, CAT_CTS_CTRL_ADR);
+ p->mp_cts_cnt = nthw_register_get_field(p->mp_cts_ctrl, CAT_CTS_CTRL_CNT);
+ p->mp_cts_data = nthw_module_get_register(p->m_cat, CAT_CTS_DATA);
+ p->mp_cts_data_cat_a = nthw_register_get_field(p->mp_cts_data, CAT_CTS_DATA_CAT_A);
+ p->mp_cts_data_cat_b = nthw_register_get_field(p->mp_cts_data, CAT_CTS_DATA_CAT_B);
+ /* COT */
+ p->mp_cot_ctrl = nthw_module_get_register(p->m_cat, CAT_COT_CTRL);
+ p->mp_cot_addr = nthw_register_get_field(p->mp_cot_ctrl, CAT_COT_CTRL_ADR);
+ p->mp_cot_cnt = nthw_register_get_field(p->mp_cot_ctrl, CAT_COT_CTRL_CNT);
+ p->mp_cot_data = nthw_module_get_register(p->m_cat, CAT_COT_DATA);
+ p->mp_cot_data_color = nthw_register_get_field(p->mp_cot_data, CAT_COT_DATA_COLOR);
+ p->mp_cot_data_km = nthw_register_get_field(p->mp_cot_data, CAT_COT_DATA_KM);
+ p->mp_cot_data_nfv_sb = nthw_register_query_field(p->mp_cot_data, CAT_COT_DATA_NFV_SB);
+ /* CCT */
+ p->mp_cct_ctrl = nthw_module_get_register(p->m_cat, CAT_CCT_CTRL);
+ p->mp_cct_addr = nthw_register_get_field(p->mp_cct_ctrl, CAT_CCT_CTRL_ADR);
+ p->mp_cct_cnt = nthw_register_get_field(p->mp_cct_ctrl, CAT_CCT_CTRL_CNT);
+ p->mp_cct_data = nthw_module_get_register(p->m_cat, CAT_CCT_DATA);
+ p->mp_cct_data_color = nthw_register_get_field(p->mp_cct_data, CAT_CCT_DATA_COLOR);
+ p->mp_cct_data_km = nthw_register_get_field(p->mp_cct_data, CAT_CCT_DATA_KM);
+ /* EXO */
+ p->mp_exo_ctrl = nthw_module_get_register(p->m_cat, CAT_EXO_CTRL);
+ p->mp_exo_addr = nthw_register_get_field(p->mp_exo_ctrl, CAT_EXO_CTRL_ADR);
+ p->mp_exo_cnt = nthw_register_get_field(p->mp_exo_ctrl, CAT_EXO_CTRL_CNT);
+ p->mp_exo_data = nthw_module_get_register(p->m_cat, CAT_EXO_DATA);
+ p->mp_exo_data_dyn = nthw_register_get_field(p->mp_exo_data, CAT_EXO_DATA_DYN);
+ p->mp_exo_data_ofs = nthw_register_get_field(p->mp_exo_data, CAT_EXO_DATA_OFS);
+ /* RCK */
+ p->mp_rck_ctrl = nthw_module_get_register(p->m_cat, CAT_RCK_CTRL);
+ p->mp_rck_addr = nthw_register_get_field(p->mp_rck_ctrl, CAT_RCK_CTRL_ADR);
+ p->mp_rck_cnt = nthw_register_get_field(p->mp_rck_ctrl, CAT_RCK_CTRL_CNT);
+ p->mp_rck_data = nthw_module_get_register(p->m_cat, CAT_RCK_DATA);
+ /* LEN */
+ p->mp_len_ctrl = nthw_module_get_register(p->m_cat, CAT_LEN_CTRL);
+ p->mp_len_addr = nthw_register_get_field(p->mp_len_ctrl, CAT_LEN_CTRL_ADR);
+ p->mp_len_cnt = nthw_register_get_field(p->mp_len_ctrl, CAT_LEN_CTRL_CNT);
+ p->mp_len_data = nthw_module_get_register(p->m_cat, CAT_LEN_DATA);
+ p->mp_len_data_lower = nthw_register_get_field(p->mp_len_data, CAT_LEN_DATA_LOWER);
+ p->mp_len_data_upper = nthw_register_get_field(p->mp_len_data, CAT_LEN_DATA_UPPER);
+ p->mp_len_data_dyn1 = nthw_register_get_field(p->mp_len_data, CAT_LEN_DATA_DYN1);
+ p->mp_len_data_dyn2 = nthw_register_get_field(p->mp_len_data, CAT_LEN_DATA_DYN2);
+ p->mp_len_data_inv = nthw_register_get_field(p->mp_len_data, CAT_LEN_DATA_INV);
+
+ p->mp_cfn_data_ptc_cfp = nthw_register_query_field(p->mp_cfn_data, CAT_CFN_DATA_PTC_CFP);
+ p->mp_cfn_data_err_l3_cs =
+ nthw_register_query_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_L3_CS);
+ p->mp_cfn_data_err_l4_cs =
+ nthw_register_query_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_L4_CS);
+ p->mp_cfn_data_err_tnl_l3_cs =
+ nthw_register_query_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_TNL_L3_CS);
+ p->mp_cfn_data_err_tnl_l4_cs =
+ nthw_register_query_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_TNL_L4_CS);
+ p->mp_cfn_data_err_ttl_exp =
+ nthw_register_query_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_TTL_EXP);
+ p->mp_cfn_data_err_tnl_ttl_exp =
+ nthw_register_query_field(p->mp_cfn_data, CAT_CFN_DATA_ERR_TNL_TTL_EXP);
+
+ p->mp_kcc_ctrl = nthw_module_query_register(p->m_cat, CAT_KCC_CTRL);
+
+ if (p->mp_kcc_ctrl != NULL) {
+ p->mp_kcc_addr = nthw_register_query_field(p->mp_kcc_ctrl, CAT_KCC_CTRL_ADR);
+ p->mp_kcc_cnt = nthw_register_query_field(p->mp_kcc_ctrl, CAT_KCC_CTRL_CNT);
+ }
+
+ p->mp_kcc_data = nthw_module_query_register(p->m_cat, CAT_KCC_DATA);
+
+ if (p->mp_kcc_data != NULL) {
+ p->mp_kcc_data_key = nthw_register_query_field(p->mp_kcc_data, CAT_KCC_DATA_KEY);
+ p->mp_kcc_data_category =
+ nthw_register_query_field(p->mp_kcc_data, CAT_KCC_DATA_CATEGORY);
+ p->mp_kcc_data_id = nthw_register_query_field(p->mp_kcc_data, CAT_KCC_DATA_ID);
+ }
+
+ return 0;
+}
+
+/* CFN */
+void cat_nthw_cfn_select(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_addr, val);
+}
+
+void cat_nthw_cfn_cnt(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_cnt, val);
+}
+
+void cat_nthw_cfn_enable(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_enable, val);
+}
+
+void cat_nthw_cfn_inv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_inv, val);
+}
+
+void cat_nthw_cfn_ptc_inv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_inv, val);
+}
+
+void cat_nthw_cfn_ptc_isl(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_isl, val);
+}
+
+void cat_nthw_cfn_ptc_mac(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_mac, val);
+}
+
+void cat_nthw_cfn_ptc_l2(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_l2, val);
+}
+
+void cat_nthw_cfn_ptc_vn_tag(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_vn_tag, val);
+}
+
+void cat_nthw_cfn_ptc_vlan(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_vlan, val);
+}
+
+void cat_nthw_cfn_ptc_mpls(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_mpls, val);
+}
+
+void cat_nthw_cfn_ptc_l3(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_l3, val);
+}
+
+void cat_nthw_cfn_ptc_frag(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_frag, val);
+}
+
+void cat_nthw_cfn_ptc_ip_prot(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_ip_prot, val);
+}
+
+void cat_nthw_cfn_ptc_l4(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_l4, val);
+}
+
+void cat_nthw_cfn_ptc_tunnel(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_tunnel, val);
+}
+
+void cat_nthw_cfn_ptc_tnl_l2(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_tnl_l2, val);
+}
+
+void cat_nthw_cfn_ptc_tnl_vlan(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_tnl_vlan, val);
+}
+
+void cat_nthw_cfn_ptc_tnl_mpls(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_tnl_mpls, val);
+}
+
+void cat_nthw_cfn_ptc_tnl_l3(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_tnl_l3, val);
+}
+
+void cat_nthw_cfn_ptc_tnl_frag(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_tnl_frag, val);
+}
+
+void cat_nthw_cfn_ptc_tnl_ip_prot(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_tnl_ip_prot, val);
+}
+
+void cat_nthw_cfn_ptc_tnl_l4(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_ptc_tnl_l4, val);
+}
+
+void cat_nthw_cfn_ptc_cfp(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cfn_data_ptc_cfp);
+ nthw_field_set_val32(p->mp_cfn_data_ptc_cfp, val);
+}
+
+void cat_nthw_cfn_err_l3_cs(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cfn_data_err_l3_cs);
+ nthw_field_set_val32(p->mp_cfn_data_err_l3_cs, val);
+}
+
+void cat_nthw_cfn_err_l4_cs(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cfn_data_err_l4_cs);
+ nthw_field_set_val32(p->mp_cfn_data_err_l4_cs, val);
+}
+
+void cat_nthw_cfn_err_tnl_l3_cs(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cfn_data_err_tnl_l3_cs);
+ nthw_field_set_val32(p->mp_cfn_data_err_tnl_l3_cs, val);
+}
+
+void cat_nthw_cfn_err_tnl_l4_cs(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cfn_data_err_tnl_l4_cs);
+ nthw_field_set_val32(p->mp_cfn_data_err_tnl_l4_cs, val);
+}
+
+void cat_nthw_cfn_err_ttl_exp(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cfn_data_err_ttl_exp);
+ nthw_field_set_val32(p->mp_cfn_data_err_ttl_exp, val);
+}
+
+void cat_nthw_cfn_err_tnl_ttl_exp(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cfn_data_err_tnl_ttl_exp);
+ nthw_field_set_val32(p->mp_cfn_data_err_tnl_ttl_exp, val);
+}
+
+void cat_nthw_cfn_err_inv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_err_inv, val);
+}
+
+void cat_nthw_cfn_err_cv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_err_cv, val);
+}
+
+void cat_nthw_cfn_err_fcs(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_err_fcs, val);
+}
+
+void cat_nthw_cfn_err_trunc(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_err_trunc, val);
+}
+
+void cat_nthw_cfn_mac_port(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_mac_port, val);
+}
+
+void cat_nthw_cfn_pm_cmp(const struct cat_nthw *p, const uint32_t *val)
+{
+ nthw_field_set_val(p->mp_cfn_data_pm_cmp, val, p->mp_cfn_data_pm_cmp->mn_words);
+}
+
+void cat_nthw_cfn_pm_dct(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_pm_dct, val);
+}
+
+void cat_nthw_cfn_pm_ext_inv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_pm_ext_inv, val);
+}
+
+void cat_nthw_cfn_pm_cmb(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_pm_cmb, val);
+}
+
+void cat_nthw_cfn_pm_and_inv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_pm_and_inv, val);
+}
+
+void cat_nthw_cfn_pm_or_inv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_pm_or_inv, val);
+}
+
+void cat_nthw_cfn_pm_inv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_pm_inv, val);
+}
+
+void cat_nthw_cfn_lc(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_lc, val);
+}
+
+void cat_nthw_cfn_lc_inv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_lc_inv, val);
+}
+
+void cat_nthw_cfn_km0_or(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cfn_data_km0_or, val);
+}
+
+void cat_nthw_cfn_km1_or(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cfn_data_km1_or);
+ nthw_field_set_val32(p->mp_cfn_data_km1_or, val);
+}
+
+void cat_nthw_cfn_flush(const struct cat_nthw *p)
+{
+ nthw_register_flush(p->mp_cfn_ctrl, 1);
+ nthw_register_flush(p->mp_cfn_data, 1);
+}
+
+void cat_nthw_kce_select(const struct cat_nthw *p, int index, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_kce_addr[index], val);
+}
+
+void cat_nthw_kce_cnt(const struct cat_nthw *p, int index, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_kce_cnt[index], val);
+}
+
+void cat_nthw_kce_enable(const struct cat_nthw *p, int index, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_kce_data_enable[index], val);
+}
+
+void cat_nthw_kce_flush(const struct cat_nthw *p, int index)
+{
+ nthw_register_flush(p->mp_kce_ctrl[index], 1);
+ nthw_register_flush(p->mp_kce_data[index], 1);
+}
+
+void cat_nthw_kcs_select(const struct cat_nthw *p, int index, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_kcs_addr[index], val);
+}
+
+void cat_nthw_kcs_cnt(const struct cat_nthw *p, int index, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_kcs_cnt[index], val);
+}
+
+void cat_nthw_kcs_category(const struct cat_nthw *p, int index, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_kcs_data_category[index], val);
+}
+
+void cat_nthw_kcs_flush(const struct cat_nthw *p, int index)
+{
+ nthw_register_flush(p->mp_kcs_ctrl[index], 1);
+ nthw_register_flush(p->mp_kcs_data[index], 1);
+}
+
+void cat_nthw_fte_select(const struct cat_nthw *p, int index, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_fte_addr[index], val);
+}
+
+void cat_nthw_fte_cnt(const struct cat_nthw *p, int index, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_fte_cnt[index], val);
+}
+
+void cat_nthw_fte_enable(const struct cat_nthw *p, int index, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_fte_data_enable[index], val);
+}
+
+void cat_nthw_fte_flush(const struct cat_nthw *p, int index)
+{
+ nthw_register_flush(p->mp_fte_ctrl[index], 1);
+ nthw_register_flush(p->mp_fte_data[index], 1);
+}
+
+void cat_nthw_cte_select(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cte_addr, val);
+}
+
+void cat_nthw_cte_cnt(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cte_cnt, val);
+}
+
+void cat_nthw_cte_enable_col(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cte_data_col, val);
+}
+
+void cat_nthw_cte_enable_cor(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cte_data_cor, val);
+}
+
+void cat_nthw_cte_enable_hsh(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cte_data_hsh, val);
+}
+
+void cat_nthw_cte_enable_qsl(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cte_data_qsl, val);
+}
+
+void cat_nthw_cte_enable_ipf(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cte_data_ipf, val);
+}
+
+void cat_nthw_cte_enable_slc(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cte_data_slc, val);
+}
+
+void cat_nthw_cte_enable_pdb(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cte_data_pdb, val);
+}
+
+void cat_nthw_cte_enable_msk(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cte_data_msk);
+ nthw_field_set_val32(p->mp_cte_data_msk, val);
+}
+
+void cat_nthw_cte_enable_hst(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cte_data_hst);
+ nthw_field_set_val32(p->mp_cte_data_hst, val);
+}
+
+void cat_nthw_cte_enable_epp(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cte_data_epp);
+ nthw_field_set_val32(p->mp_cte_data_epp, val);
+}
+
+void cat_nthw_cte_enable_tpe(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_cte_data_tpe);
+ nthw_field_set_val32(p->mp_cte_data_tpe, val);
+}
+
+void cat_nthw_cte_flush(const struct cat_nthw *p)
+{
+ nthw_register_flush(p->mp_cte_ctrl, 1);
+ nthw_register_flush(p->mp_cte_data, 1);
+}
+
+void cat_nthw_cts_select(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cts_addr, val);
+}
+
+void cat_nthw_cts_cnt(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cts_cnt, val);
+}
+
+void cat_nthw_cts_cat_a(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cts_data_cat_a, val);
+}
+
+void cat_nthw_cts_cat_b(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cts_data_cat_b, val);
+}
+
+void cat_nthw_cts_flush(const struct cat_nthw *p)
+{
+ nthw_register_flush(p->mp_cts_ctrl, 1);
+ nthw_register_flush(p->mp_cts_data, 1);
+}
+
+void cat_nthw_cot_select(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cot_addr, val);
+}
+
+void cat_nthw_cot_cnt(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cot_cnt, val);
+}
+
+void cat_nthw_cot_color(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cot_data_color, val);
+}
+
+void cat_nthw_cot_km(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cot_data_km, val);
+}
+
+void cat_nthw_cot_flush(const struct cat_nthw *p)
+{
+ nthw_register_flush(p->mp_cot_ctrl, 1);
+ nthw_register_flush(p->mp_cot_data, 1);
+}
+
+void cat_nthw_cct_select(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cct_addr, val);
+}
+
+void cat_nthw_cct_cnt(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cct_cnt, val);
+}
+
+void cat_nthw_cct_color(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cct_data_color, val);
+}
+
+void cat_nthw_cct_km(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_cct_data_km, val);
+}
+
+void cat_nthw_cct_flush(const struct cat_nthw *p)
+{
+ nthw_register_flush(p->mp_cct_ctrl, 1);
+ nthw_register_flush(p->mp_cct_data, 1);
+}
+
+void cat_nthw_exo_select(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_exo_addr, val);
+}
+
+void cat_nthw_exo_cnt(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_exo_cnt, val);
+}
+
+void cat_nthw_exo_dyn(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_exo_data_dyn, val);
+}
+
+void cat_nthw_exo_ofs(const struct cat_nthw *p, int32_t val)
+{
+ nthw_field_set_val32(p->mp_exo_data_ofs, val);
+}
+
+void cat_nthw_exo_flush(const struct cat_nthw *p)
+{
+ nthw_register_flush(p->mp_exo_ctrl, 1);
+ nthw_register_flush(p->mp_exo_data, 1);
+}
+
+void cat_nthw_rck_select(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_rck_addr, val);
+}
+
+void cat_nthw_rck_cnt(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_rck_cnt, val);
+}
+
+void cat_nthw_rck_data(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_register_set_val(p->mp_rck_data, &val, 1);
+ nthw_register_make_dirty(p->mp_rck_data);
+}
+
+void cat_nthw_rck_flush(const struct cat_nthw *p)
+{
+ nthw_register_flush(p->mp_rck_ctrl, 1);
+ nthw_register_flush(p->mp_rck_data, 1);
+}
+
+void cat_nthw_len_select(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_len_addr, val);
+}
+
+void cat_nthw_len_cnt(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_len_cnt, val);
+}
+
+void cat_nthw_len_lower(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_len_data_lower, val);
+}
+
+void cat_nthw_len_upper(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_len_data_upper, val);
+}
+
+void cat_nthw_len_dyn1(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_len_data_dyn1, val);
+}
+
+void cat_nthw_len_dyn2(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_len_data_dyn2, val);
+}
+
+void cat_nthw_len_inv(const struct cat_nthw *p, uint32_t val)
+{
+ nthw_field_set_val32(p->mp_len_data_inv, val);
+}
+
+void cat_nthw_len_flush(const struct cat_nthw *p)
+{
+ nthw_register_flush(p->mp_len_ctrl, 1);
+ nthw_register_flush(p->mp_len_data, 1);
+}
+
+void cat_nthw_kcc_select(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_kcc_addr);
+ nthw_field_set_val32(p->mp_kcc_addr, val);
+}
+
+void cat_nthw_kcc_cnt(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_kcc_cnt);
+ nthw_field_set_val32(p->mp_kcc_cnt, val);
+}
+
+void cat_nthw_kcc_key(const struct cat_nthw *p, uint32_t *val)
+{
+ assert(p->mp_kcc_data_key);
+ nthw_field_set_val(p->mp_kcc_data_key, val, 2);
+}
+
+void cat_nthw_kcc_category(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_kcc_data_category);
+ nthw_field_set_val32(p->mp_kcc_data_category, val);
+}
+
+void cat_nthw_kcc_id(const struct cat_nthw *p, uint32_t val)
+{
+ assert(p->mp_kcc_data_id);
+ nthw_field_set_val32(p->mp_kcc_data_id, val);
+}
+
+void cat_nthw_kcc_flush(const struct cat_nthw *p)
+{
+ assert(p->mp_kcc_ctrl);
+ assert(p->mp_kcc_data);
+ nthw_register_flush(p->mp_kcc_ctrl, 1);
+ nthw_register_flush(p->mp_kcc_data, 1);
+}
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.h
new file mode 100644
index 0000000000..29f9a332f1
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_cat.h
@@ -0,0 +1,291 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __FLOW_NTHW_CAT_H__
+#define __FLOW_NTHW_CAT_H__
+
+#include <stdint.h>
+
+#include "nthw_fpga_model.h"
+
+struct cat_nthw;
+
+typedef struct cat_nthw cat_nthw_t;
+
+struct cat_nthw *cat_nthw_new(void);
+void cat_nthw_delete(struct cat_nthw *p);
+int cat_nthw_init(struct cat_nthw *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int cat_nthw_setup(struct cat_nthw *p, int n_idx, int n_idx_cnt);
+void cat_nthw_set_debug_mode(struct cat_nthw *p, unsigned int n_debug_mode);
+
+/* CFN */
+void cat_nthw_cfn_select(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_cnt(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_enable(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_inv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_inv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_isl(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_cfp(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_mac(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_l2(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_vn_tag(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_vlan(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_mpls(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_l3(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_frag(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_ip_prot(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_l4(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_tunnel(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_tnl_l2(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_tnl_vlan(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_tnl_mpls(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_tnl_l3(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_tnl_frag(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_tnl_ip_prot(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_ptc_tnl_l4(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_inv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_cv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_fcs(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_trunc(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_l3_cs(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_l4_cs(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_tnl_l3_cs(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_tnl_l4_cs(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_ttl_exp(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_err_tnl_ttl_exp(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_mac_port(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_pm_cmp(const struct cat_nthw *p, const uint32_t *val);
+void cat_nthw_cfn_pm_dct(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_pm_ext_inv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_pm_cmb(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_pm_and_inv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_pm_or_inv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_pm_inv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_lc(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_lc_inv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_km0_or(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_km1_or(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cfn_flush(const struct cat_nthw *p);
+/* KCE 0/1 */
+void cat_nthw_kce_select(const struct cat_nthw *p, int index, uint32_t val);
+void cat_nthw_kce_cnt(const struct cat_nthw *p, int index, uint32_t val);
+void cat_nthw_kce_enable(const struct cat_nthw *p, int index, uint32_t val);
+void cat_nthw_kce_flush(const struct cat_nthw *p, int index);
+/* KCS 0/1 */
+void cat_nthw_kcs_select(const struct cat_nthw *p, int index, uint32_t val);
+void cat_nthw_kcs_cnt(const struct cat_nthw *p, int index, uint32_t val);
+void cat_nthw_kcs_category(const struct cat_nthw *p, int index, uint32_t val);
+void cat_nthw_kcs_flush(const struct cat_nthw *p, int index);
+/* FTE 0/1 */
+void cat_nthw_fte_select(const struct cat_nthw *p, int index, uint32_t val);
+void cat_nthw_fte_cnt(const struct cat_nthw *p, int index, uint32_t val);
+void cat_nthw_fte_enable(const struct cat_nthw *p, int index, uint32_t val);
+void cat_nthw_fte_flush(const struct cat_nthw *p, int index);
+/* CTE */
+void cat_nthw_cte_select(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_cnt(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_col(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_cor(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_hsh(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_qsl(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_ipf(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_slc(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_pdb(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_msk(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_hst(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_epp(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_enable_tpe(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cte_flush(const struct cat_nthw *p);
+/* CTS */
+void cat_nthw_cts_select(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cts_cnt(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cts_flush(const struct cat_nthw *p);
+void cat_nthw_cts_cat_a(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cts_cat_b(const struct cat_nthw *p, uint32_t val);
+/* COT */
+void cat_nthw_cot_select(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cot_cnt(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cot_color(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cot_km(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cot_flush(const struct cat_nthw *p);
+/* CCT */
+void cat_nthw_cct_select(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cct_cnt(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cct_color(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cct_km(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_cct_flush(const struct cat_nthw *p);
+/* EXO */
+void cat_nthw_exo_select(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_exo_cnt(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_exo_dyn(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_exo_ofs(const struct cat_nthw *p, int32_t val);
+void cat_nthw_exo_flush(const struct cat_nthw *p);
+/* RCK */
+void cat_nthw_rck_select(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_rck_cnt(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_rck_data(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_rck_flush(const struct cat_nthw *p);
+/* LEN */
+void cat_nthw_len_select(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_len_cnt(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_len_lower(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_len_upper(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_len_dyn1(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_len_dyn2(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_len_inv(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_len_flush(const struct cat_nthw *p);
+/* KCC */
+void cat_nthw_kcc_select(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_kcc_cnt(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_kcc_key(const struct cat_nthw *p, uint32_t *val);
+void cat_nthw_kcc_category(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_kcc_id(const struct cat_nthw *p, uint32_t val);
+void cat_nthw_kcc_flush(const struct cat_nthw *p);
+
+struct cat_nthw {
+ uint8_t m_physical_adapter_no;
+ nthw_fpga_t *mp_fpga;
+ nthw_module_t *m_cat;
+ int m_km_if_cnt;
+
+ nthw_register_t *mp_cfn_ctrl;
+ nthw_field_t *mp_cfn_addr;
+ nthw_field_t *mp_cfn_cnt;
+ nthw_register_t *mp_cfn_data;
+ nthw_field_t *mp_cfn_data_enable;
+ nthw_field_t *mp_cfn_data_inv;
+ nthw_field_t *mp_cfn_data_ptc_inv;
+ nthw_field_t *mp_cfn_data_ptc_isl;
+ nthw_field_t *mp_cfn_data_ptc_cfp;
+ nthw_field_t *mp_cfn_data_ptc_mac;
+ nthw_field_t *mp_cfn_data_ptc_l2;
+ nthw_field_t *mp_cfn_data_ptc_vn_tag;
+ nthw_field_t *mp_cfn_data_ptc_vlan;
+ nthw_field_t *mp_cfn_data_ptc_mpls;
+ nthw_field_t *mp_cfn_data_ptc_l3;
+ nthw_field_t *mp_cfn_data_ptc_frag;
+ nthw_field_t *mp_cfn_data_ptc_ip_prot;
+ nthw_field_t *mp_cfn_data_ptc_l4;
+ nthw_field_t *mp_cfn_data_ptc_tunnel;
+ nthw_field_t *mp_cfn_data_ptc_tnl_l2;
+ nthw_field_t *mp_cfn_data_ptc_tnl_vlan;
+ nthw_field_t *mp_cfn_data_ptc_tnl_mpls;
+ nthw_field_t *mp_cfn_data_ptc_tnl_l3;
+ nthw_field_t *mp_cfn_data_ptc_tnl_frag;
+ nthw_field_t *mp_cfn_data_ptc_tnl_ip_prot;
+ nthw_field_t *mp_cfn_data_ptc_tnl_l4;
+ nthw_field_t *mp_cfn_data_err_inv;
+ nthw_field_t *mp_cfn_data_err_cv;
+ nthw_field_t *mp_cfn_data_err_fcs;
+ nthw_field_t *mp_cfn_data_err_trunc;
+ nthw_field_t *mp_cfn_data_err_l3_cs;
+ nthw_field_t *mp_cfn_data_err_l4_cs;
+ nthw_field_t *mp_cfn_data_err_tnl_l3_cs;
+ nthw_field_t *mp_cfn_data_err_tnl_l4_cs;
+ nthw_field_t *mp_cfn_data_err_ttl_exp;
+ nthw_field_t *mp_cfn_data_err_tnl_ttl_exp;
+ nthw_field_t *mp_cfn_data_mac_port;
+ nthw_field_t *mp_cfn_data_pm_cmp;
+ nthw_field_t *mp_cfn_data_pm_dct;
+ nthw_field_t *mp_cfn_data_pm_ext_inv;
+ nthw_field_t *mp_cfn_data_pm_cmb;
+ nthw_field_t *mp_cfn_data_pm_and_inv;
+ nthw_field_t *mp_cfn_data_pm_or_inv;
+ nthw_field_t *mp_cfn_data_pm_inv;
+ nthw_field_t *mp_cfn_data_lc;
+ nthw_field_t *mp_cfn_data_lc_inv;
+ nthw_field_t *mp_cfn_data_km0_or;
+ nthw_field_t *mp_cfn_data_km1_or;
+
+ nthw_register_t *mp_kce_ctrl[2];
+ nthw_field_t *mp_kce_addr[2];
+ nthw_field_t *mp_kce_cnt[2];
+ nthw_register_t *mp_kce_data[2];
+ nthw_field_t *mp_kce_data_enable[2];
+
+ nthw_register_t *mp_kcs_ctrl[2];
+ nthw_field_t *mp_kcs_addr[2];
+ nthw_field_t *mp_kcs_cnt[2];
+ nthw_register_t *mp_kcs_data[2];
+ nthw_field_t *mp_kcs_data_category[2];
+
+ nthw_register_t *mp_fte_ctrl[2];
+ nthw_field_t *mp_fte_addr[2];
+ nthw_field_t *mp_fte_cnt[2];
+ nthw_register_t *mp_fte_data[2];
+ nthw_field_t *mp_fte_data_enable[2];
+
+ nthw_register_t *mp_cte_ctrl;
+ nthw_field_t *mp_cte_addr;
+ nthw_field_t *mp_cte_cnt;
+ nthw_register_t *mp_cte_data;
+ nthw_field_t *mp_cte_data_col;
+ nthw_field_t *mp_cte_data_cor;
+ nthw_field_t *mp_cte_data_hsh;
+ nthw_field_t *mp_cte_data_qsl;
+ nthw_field_t *mp_cte_data_ipf;
+ nthw_field_t *mp_cte_data_slc;
+ nthw_field_t *mp_cte_data_pdb;
+ nthw_field_t *mp_cte_data_msk;
+ nthw_field_t *mp_cte_data_hst;
+ nthw_field_t *mp_cte_data_epp;
+ nthw_field_t *mp_cte_data_tpe;
+ nthw_field_t *mp_cte_data_rrb;
+
+ nthw_register_t *mp_cts_ctrl;
+ nthw_field_t *mp_cts_addr;
+ nthw_field_t *mp_cts_cnt;
+ nthw_register_t *mp_cts_data;
+ nthw_field_t *mp_cts_data_cat_a;
+ nthw_field_t *mp_cts_data_cat_b;
+
+ nthw_register_t *mp_cot_ctrl;
+ nthw_field_t *mp_cot_addr;
+ nthw_field_t *mp_cot_cnt;
+ nthw_register_t *mp_cot_data;
+ nthw_field_t *mp_cot_data_color;
+ nthw_field_t *mp_cot_data_km;
+ nthw_field_t *mp_cot_data_nfv_sb;
+
+ nthw_register_t *mp_cct_ctrl;
+ nthw_field_t *mp_cct_addr;
+ nthw_field_t *mp_cct_cnt;
+ nthw_register_t *mp_cct_data;
+ nthw_field_t *mp_cct_data_color;
+ nthw_field_t *mp_cct_data_km;
+
+ nthw_register_t *mp_exo_ctrl;
+ nthw_field_t *mp_exo_addr;
+ nthw_field_t *mp_exo_cnt;
+ nthw_register_t *mp_exo_data;
+ nthw_field_t *mp_exo_data_dyn;
+ nthw_field_t *mp_exo_data_ofs;
+
+ nthw_register_t *mp_rck_ctrl;
+ nthw_field_t *mp_rck_addr;
+ nthw_field_t *mp_rck_cnt;
+ nthw_register_t *mp_rck_data;
+
+ nthw_register_t *mp_len_ctrl;
+ nthw_field_t *mp_len_addr;
+ nthw_field_t *mp_len_cnt;
+ nthw_register_t *mp_len_data;
+ nthw_field_t *mp_len_data_lower;
+ nthw_field_t *mp_len_data_upper;
+ nthw_field_t *mp_len_data_dyn1;
+ nthw_field_t *mp_len_data_dyn2;
+ nthw_field_t *mp_len_data_inv;
+ nthw_register_t *mp_kcc_ctrl;
+ nthw_field_t *mp_kcc_addr;
+ nthw_field_t *mp_kcc_cnt;
+
+ nthw_register_t *mp_kcc_data;
+ nthw_field_t *mp_kcc_data_key;
+ nthw_field_t *mp_kcc_data_category;
+ nthw_field_t *mp_kcc_data_id;
+};
+
+#endif /* __FLOW_NTHW_CAT_H__ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
index 0b69d09cde..d4ccc5157d 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
@@ -14,6 +14,7 @@
#define _NTHW_FPGA_MOD_DEFS_H_
#define MOD_UNKNOWN (0L)/* Unknown/uninitialized - keep this as the first element */
+#define MOD_CAT (0x30b447c2UL)
#define MOD_GFG (0xfc423807UL)
#define MOD_GMF (0x68b1d15aUL)
#define MOD_GPIO_PHY (0xbbe81659UL)
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
index 8a55b9aeca..dad498256f 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
@@ -13,6 +13,7 @@
#ifndef _NTHW_FPGA_REG_DEFS_
#define _NTHW_FPGA_REG_DEFS_
+#include "nthw_fpga_reg_defs_cat.h"
#include "nthw_fpga_reg_defs_gfg.h"
#include "nthw_fpga_reg_defs_gmf.h"
#include "nthw_fpga_reg_defs_gpio_phy.h"
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
new file mode 100644
index 0000000000..cafed8a4bc
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
@@ -0,0 +1,238 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+/*
+ * nthw_fpga_reg_defs_cat.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_CAT_
+#define _NTHW_FPGA_REG_DEFS_CAT_
+
+/* CAT */
+#define NTHW_MOD_CAT (0x30b447c2UL)
+#define CAT_CCT_CTRL (0x234d3a78UL)
+#define CAT_CCT_CTRL_ADR (0x6146f230UL)
+#define CAT_CCT_CTRL_CNT (0x714e6be1UL)
+#define CAT_CCT_DATA (0x8c9cb861UL)
+#define CAT_CCT_DATA_COLOR (0x27e29b73UL)
+#define CAT_CCT_DATA_KM (0x4ac2435fUL)
+#define CAT_CFN_CTRL (0xd3383422UL)
+#define CAT_CFN_CTRL_ADR (0x209d4f53UL)
+#define CAT_CFN_CTRL_CNT (0x3095d682UL)
+#define CAT_CFN_DATA (0x7ce9b63bUL)
+#define CAT_CFN_DATA_ENABLE (0xd2ae88e2UL)
+#define CAT_CFN_DATA_ERR_CV (0x22ca6722UL)
+#define CAT_CFN_DATA_ERR_FCS (0xc45c40bfUL)
+#define CAT_CFN_DATA_ERR_INV (0xac48d40UL)
+#define CAT_CFN_DATA_ERR_L3_CS (0x55fb7895UL)
+#define CAT_CFN_DATA_ERR_L4_CS (0xc82c402cUL)
+#define CAT_CFN_DATA_ERR_TNL_L3_CS (0x51e668edUL)
+#define CAT_CFN_DATA_ERR_TNL_L4_CS (0xcc315054UL)
+#define CAT_CFN_DATA_ERR_TNL_TTL_EXP (0x948d9686UL)
+#define CAT_CFN_DATA_ERR_TRUNC (0x237fdf4fUL)
+#define CAT_CFN_DATA_ERR_TTL_EXP (0x6edc7101UL)
+#define CAT_CFN_DATA_FLM_OR (0xd82cf0b3UL)
+#define CAT_CFN_DATA_INV (0xc2e6afa4UL)
+#define CAT_CFN_DATA_KM0_OR (0xc087b29cUL)
+#define CAT_CFN_DATA_KM1_OR (0x783bd5f9UL)
+#define CAT_CFN_DATA_KM_OR (0x58fbb39eUL)
+#define CAT_CFN_DATA_LC (0x3dfcfb34UL)
+#define CAT_CFN_DATA_LC_INV (0x72af18aUL)
+#define CAT_CFN_DATA_MAC_PORT (0xcd340483UL)
+#define CAT_CFN_DATA_PM_AND_INV (0x3ae1c6afUL)
+#define CAT_CFN_DATA_PM_CMB (0xf06e8f63UL)
+#define CAT_CFN_DATA_PM_CMP (0x3d7fe2bUL)
+#define CAT_CFN_DATA_PM_DCT (0x9f760139UL)
+#define CAT_CFN_DATA_PM_EXT_INV (0x7bc194b8UL)
+#define CAT_CFN_DATA_PM_INV (0xcc0e8d0bUL)
+#define CAT_CFN_DATA_PM_OR_INV (0x7790b2fUL)
+#define CAT_CFN_DATA_PTC_CFP (0x98d6c9edUL)
+#define CAT_CFN_DATA_PTC_FRAG (0x9bb1ab3cUL)
+#define CAT_CFN_DATA_PTC_INV (0xb4fb6306UL)
+#define CAT_CFN_DATA_PTC_IP_PROT (0xfee4889bUL)
+#define CAT_CFN_DATA_PTC_ISL (0xb6f5f660UL)
+#define CAT_CFN_DATA_PTC_L2 (0xdb7388deUL)
+#define CAT_CFN_DATA_PTC_L3 (0xac74b848UL)
+#define CAT_CFN_DATA_PTC_L4 (0x32102debUL)
+#define CAT_CFN_DATA_PTC_MAC (0x59b733feUL)
+#define CAT_CFN_DATA_PTC_MPLS (0xe0405263UL)
+#define CAT_CFN_DATA_PTC_TNL_FRAG (0x76e4a788UL)
+#define CAT_CFN_DATA_PTC_TNL_IP_PROT (0x8b0734cdUL)
+#define CAT_CFN_DATA_PTC_TNL_L2 (0xec64285eUL)
+#define CAT_CFN_DATA_PTC_TNL_L3 (0x9b6318c8UL)
+#define CAT_CFN_DATA_PTC_TNL_L4 (0x5078d6bUL)
+#define CAT_CFN_DATA_PTC_TNL_MPLS (0xd155ed7UL)
+#define CAT_CFN_DATA_PTC_TNL_VLAN (0x4999c6c9UL)
+#define CAT_CFN_DATA_PTC_TUNNEL (0x2ac66873UL)
+#define CAT_CFN_DATA_PTC_VLAN (0xa4ccca7dUL)
+#define CAT_CFN_DATA_PTC_VNTAG (0x23d64f2aUL)
+#define CAT_COT_CTRL (0xe4ed500cUL)
+#define CAT_COT_CTRL_ADR (0x6b5c60f7UL)
+#define CAT_COT_CTRL_CNT (0x7b54f926UL)
+#define CAT_COT_DATA (0x4b3cd215UL)
+#define CAT_COT_DATA_COLOR (0xbd582288UL)
+#define CAT_COT_DATA_KM (0x50fea3d1UL)
+#define CAT_COT_DATA_NFV_SB (0x2219c864UL)
+#define CAT_CTE_CTRL (0x49be4906UL)
+#define CAT_CTE_CTRL_ADR (0x2ee7c9aeUL)
+#define CAT_CTE_CTRL_CNT (0x3eef507fUL)
+#define CAT_CTE_DATA (0xe66fcb1fUL)
+#define CAT_CTE_DATA_COL_ENABLE (0xa9ca226bUL)
+#define CAT_CTE_DATA_COR_ENABLE (0xc0fb0172UL)
+#define CAT_CTE_DATA_EPP_ENABLE (0xfcb9fbe8UL)
+#define CAT_CTE_DATA_HSH_ENABLE (0x9f946603UL)
+#define CAT_CTE_DATA_HST_ENABLE (0xb4804267UL)
+#define CAT_CTE_DATA_IPF_ENABLE (0x5c5123caUL)
+#define CAT_CTE_DATA_MSK_ENABLE (0xf732aaa4UL)
+#define CAT_CTE_DATA_PDB_ENABLE (0xf28c946fUL)
+#define CAT_CTE_DATA_QSL_ENABLE (0xc065c2dbUL)
+#define CAT_CTE_DATA_SLC_ENABLE (0x6ec98deaUL)
+#define CAT_CTE_DATA_TPE_ENABLE (0x8e2e71UL)
+#define CAT_CTE_DATA_TX_INS_ENABLE (0x585922e3UL)
+#define CAT_CTE_DATA_TX_RPL_ENABLE (0x468ee298UL)
+#define CAT_CTS_CTRL (0x9c31a880UL)
+#define CAT_CTS_CTRL_ADR (0x4573801UL)
+#define CAT_CTS_CTRL_CNT (0x145fa1d0UL)
+#define CAT_CTS_DATA (0x33e02a99UL)
+#define CAT_CTS_DATA_CAT_A (0xa698040aUL)
+#define CAT_CTS_DATA_CAT_B (0x3f9155b0UL)
+#define CAT_DCT_CTRL (0x29883361UL)
+#define CAT_DCT_CTRL_ADR (0x15de1bbfUL)
+#define CAT_DCT_CTRL_CNT (0x5d6826eUL)
+#define CAT_DCT_DATA (0x8659b178UL)
+#define CAT_DCT_DATA_RES (0x74489a9dUL)
+#define CAT_DCT_SEL (0xeb603410UL)
+#define CAT_DCT_SEL_LU (0x60e126beUL)
+#define CAT_EXO_CTRL (0xe9ea0993UL)
+#define CAT_EXO_CTRL_ADR (0xdce26e40UL)
+#define CAT_EXO_CTRL_CNT (0xcceaf791UL)
+#define CAT_EXO_DATA (0x463b8b8aUL)
+#define CAT_EXO_DATA_DYN (0x20ae0124UL)
+#define CAT_EXO_DATA_OFS (0x82a78c82UL)
+#define CAT_FCE_CTRL (0xa327e522UL)
+#define CAT_FCE_CTRL_ADR (0x31896ff6UL)
+#define CAT_FCE_CTRL_CNT (0x2181f627UL)
+#define CAT_FCE_DATA (0xcf6673bUL)
+#define CAT_FCE_DATA_ENABLE (0x8243e7a7UL)
+#define CAT_FCS_CTRL (0x76a804a4UL)
+#define CAT_FCS_CTRL_ADR (0x1b399e59UL)
+#define CAT_FCS_CTRL_CNT (0xb310788UL)
+#define CAT_FCS_DATA (0xd97986bdUL)
+#define CAT_FCS_DATA_CATEGORY (0x69d964f3UL)
+#define CAT_FTE0_CTRL (0x4f655742UL)
+#define CAT_FTE0_CTRL_ADR (0xa786315fUL)
+#define CAT_FTE0_CTRL_CNT (0xb78ea88eUL)
+#define CAT_FTE0_DATA (0xe0b4d55bUL)
+#define CAT_FTE0_DATA_ENABLE (0xe06dec95UL)
+#define CAT_FTE1_CTRL (0x843984e7UL)
+#define CAT_FTE1_CTRL_ADR (0x48445a61UL)
+#define CAT_FTE1_CTRL_CNT (0x584cc3b0UL)
+#define CAT_FTE1_DATA (0x2be806feUL)
+#define CAT_FTE1_DATA_ENABLE (0x3dfb3510UL)
+#define CAT_FTE_CTRL (0x15e4762UL)
+#define CAT_FTE_CTRL_ADR (0xb644bebeUL)
+#define CAT_FTE_CTRL_CNT (0xa64c276fUL)
+#define CAT_FTE_DATA (0xae8fc57bUL)
+#define CAT_FTE_DATA_ENABLE (0x813c710bUL)
+#define CAT_FTE_FLM_CTRL (0x4a63f99eUL)
+#define CAT_FTE_FLM_CTRL_ADR (0x3ed2141dUL)
+#define CAT_FTE_FLM_CTRL_CNT (0x2eda8dccUL)
+#define CAT_FTE_FLM_DATA (0xe5b27b87UL)
+#define CAT_FTE_FLM_DATA_ENABLE (0x1786f0a8UL)
+#define CAT_JOIN (0xf643707UL)
+#define CAT_JOIN_J1 (0x494d06b2UL)
+#define CAT_JOIN_J2 (0xd0445708UL)
+#define CAT_KCC (0x26068f04UL)
+#define CAT_KCC_CTRL (0xee7b13eeUL)
+#define CAT_KCC_CTRL_ADR (0xa2381e5fUL)
+#define CAT_KCC_CTRL_CNT (0xb230878eUL)
+#define CAT_KCC_DATA (0x41aa91f7UL)
+#define CAT_KCC_DATA_CATEGORY (0x3f0558aeUL)
+#define CAT_KCC_DATA_ID (0x734a5784UL)
+#define CAT_KCC_DATA_KEY (0x308cee9cUL)
+#define CAT_KCE0_CTRL (0xc8548827UL)
+#define CAT_KCE0_CTRL_ADR (0x982a5552UL)
+#define CAT_KCE0_CTRL_CNT (0x8822cc83UL)
+#define CAT_KCE0_DATA (0x67850a3eUL)
+#define CAT_KCE0_DATA_ENABLE (0x36443e99UL)
+#define CAT_KCE1_CTRL (0x3085b82UL)
+#define CAT_KCE1_CTRL_ADR (0x77e83e6cUL)
+#define CAT_KCE1_CTRL_CNT (0x67e0a7bdUL)
+#define CAT_KCE1_DATA (0xacd9d99bUL)
+#define CAT_KCE1_DATA_ENABLE (0xebd2e71cUL)
+#define CAT_KCE_CTRL (0x3822f0f3UL)
+#define CAT_KCE_CTRL_ADR (0xaf266e18UL)
+#define CAT_KCE_CTRL_CNT (0xbf2ef7c9UL)
+#define CAT_KCE_DATA (0x97f372eaUL)
+#define CAT_KCE_DATA_ENABLE (0x7e4d95abUL)
+#define CAT_KCS0_CTRL (0xcc5a21d3UL)
+#define CAT_KCS0_CTRL_ADR (0xde695bdaUL)
+#define CAT_KCS0_CTRL_CNT (0xce61c20bUL)
+#define CAT_KCS0_DATA (0x638ba3caUL)
+#define CAT_KCS0_DATA_CATEGORY (0x43dbd3eUL)
+#define CAT_KCS1_CTRL (0x706f276UL)
+#define CAT_KCS1_CTRL_ADR (0x31ab30e4UL)
+#define CAT_KCS1_CTRL_CNT (0x21a3a935UL)
+#define CAT_KCS1_DATA (0xa8d7706fUL)
+#define CAT_KCS1_DATA_CATEGORY (0xbdc666d6UL)
+#define CAT_KCS_CTRL (0xedad1175UL)
+#define CAT_KCS_CTRL_ADR (0x85969fb7UL)
+#define CAT_KCS_CTRL_CNT (0x959e0666UL)
+#define CAT_KCS_DATA (0x427c936cUL)
+#define CAT_KCS_DATA_CATEGORY (0x7b67c7e1UL)
+#define CAT_LEN_CTRL (0x3bf03c13UL)
+#define CAT_LEN_CTRL_ADR (0xcbebb623UL)
+#define CAT_LEN_CTRL_CNT (0xdbe32ff2UL)
+#define CAT_LEN_DATA (0x9421be0aUL)
+#define CAT_LEN_DATA_DYN1 (0x6b539c5dUL)
+#define CAT_LEN_DATA_DYN2 (0xf25acde7UL)
+#define CAT_LEN_DATA_INV (0x299056d4UL)
+#define CAT_LEN_DATA_LOWER (0x5f70c60fUL)
+#define CAT_LEN_DATA_UPPER (0x3fb562b0UL)
+#define CAT_RCK_CTRL (0x61dcbb83UL)
+#define CAT_RCK_CTRL_ADR (0x205e89c6UL)
+#define CAT_RCK_CTRL_CNT (0x30561017UL)
+#define CAT_RCK_DATA (0xce0d399aUL)
+#define CAT_RCK_DATA_CM0U (0xc643fdb9UL)
+#define CAT_RCK_DATA_CM1U (0xdf58ccf8UL)
+#define CAT_RCK_DATA_CM2U (0xf4759f3bUL)
+#define CAT_RCK_DATA_CM3U (0xed6eae7aUL)
+#define CAT_RCK_DATA_CM4U (0xa22f38bdUL)
+#define CAT_RCK_DATA_CM5U (0xbb3409fcUL)
+#define CAT_RCK_DATA_CM6U (0x90195a3fUL)
+#define CAT_RCK_DATA_CM7U (0x89026b7eUL)
+#define CAT_RCK_DATA_CML0 (0x78115e94UL)
+#define CAT_RCK_DATA_CML1 (0xf166e02UL)
+#define CAT_RCK_DATA_CML2 (0x961f3fb8UL)
+#define CAT_RCK_DATA_CML3 (0xe1180f2eUL)
+#define CAT_RCK_DATA_CML4 (0x7f7c9a8dUL)
+#define CAT_RCK_DATA_CML5 (0x87baa1bUL)
+#define CAT_RCK_DATA_CML6 (0x9172fba1UL)
+#define CAT_RCK_DATA_CML7 (0xe675cb37UL)
+#define CAT_RCK_DATA_SEL0 (0x261b58b3UL)
+#define CAT_RCK_DATA_SEL1 (0x511c6825UL)
+#define CAT_RCK_DATA_SEL2 (0xc815399fUL)
+#define CAT_RCK_DATA_SEL3 (0xbf120909UL)
+#define CAT_RCK_DATA_SEL4 (0x21769caaUL)
+#define CAT_RCK_DATA_SEL5 (0x5671ac3cUL)
+#define CAT_RCK_DATA_SEL6 (0xcf78fd86UL)
+#define CAT_RCK_DATA_SEL7 (0xb87fcd10UL)
+#define CAT_RCK_DATA_SEU0 (0xbd1bf1abUL)
+#define CAT_RCK_DATA_SEU1 (0xca1cc13dUL)
+#define CAT_RCK_DATA_SEU2 (0x53159087UL)
+#define CAT_RCK_DATA_SEU3 (0x2412a011UL)
+#define CAT_RCK_DATA_SEU4 (0xba7635b2UL)
+#define CAT_RCK_DATA_SEU5 (0xcd710524UL)
+#define CAT_RCK_DATA_SEU6 (0x5478549eUL)
+#define CAT_RCK_DATA_SEU7 (0x237f6408UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_CAT_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
--
2.45.0
next prev parent reply other threads:[~2024-10-06 20:39 UTC|newest]
Thread overview: 161+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-06 20:36 [PATCH v1 00/50] Provide: flow filter init API, Enable virtual queues, fix ntnic issues for release 24.07 Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 01/50] net/ntnic: update NT NiC PMD driver with FPGA version Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 00/50] Provide: flow filter init API, Enable virtual queues, fix ntnic issues for release 24.07 Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 01/50] net/ntnic: update NT NiC PMD driver with FPGA version Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 02/50] net/ntnic: fix coverity issues: Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 03/50] net/ntnic: update documentation Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 04/50] net/ntnic: remove extra calling of the API for release port Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 05/50] net/ntnic: extend and fix logging implementation Serhii Iliushyk
2024-10-09 3:19 ` Ferruh Yigit
2024-10-07 19:33 ` [PATCH v2 06/50] net/ntnic: add flow filter init API Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 07/50] net/ntnic: add flow filter deinitialization API Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 08/50] net/ntnic: add flow backend initialization API Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 09/50] net/ntnic: add flow backend deinitialization API Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 10/50] net/ntnic: add INFO flow module Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 11/50] net/ntnic: add categorizer (CAT) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 12/50] net/ntnic: add key match (KM) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 13/50] net/ntnic: add flow matcher (FLM) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 14/50] net/ntnic: add IP fragmenter (IFR) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 15/50] net/ntnic: add hasher (HSH) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 16/50] net/ntnic: add queue select (QSL) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 17/50] net/ntnic: add slicer (SLC LR) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 18/50] net/ntnic: add packet descriptor builder (PDB) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 19/50] net/ntnic: add header field update (HFU) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 20/50] net/ntnic: add RPP local retransmit (RPP LR) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 21/50] net/ntnic: add copier (Tx CPY) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 22/50] net/ntnic: add checksum update (CSU) " Serhii Iliushyk
2024-10-07 19:33 ` [PATCH v2 23/50] net/ntnic: add insert (Tx INS) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 24/50] net/ntnic: add replacer (Tx RPL) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 25/50] net/ntnic: add Tx Packet Editor (TPE) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 26/50] net/ntnic: add base init and deinit of the NT flow API Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 27/50] net/ntnic: add base init and deinit the NT flow backend Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 28/50] net/ntnic: add categorizer (CAT) FPGA module Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 29/50] net/ntnic: add key match (KM) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 30/50] net/ntnic: add flow matcher (FLM) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 31/50] net/ntnic: add hasher (HSH) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 32/50] net/ntnic: add queue select (QSL) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 33/50] net/ntnic: add slicer (SLC LR) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 34/50] net/ntnic: add packet descriptor builder (PDB) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 35/50] net/ntnic: add Tx Packet Editor (TPE) " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 36/50] net/ntnic: add receive MAC converter (RMC) core module Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 37/50] net/ntnic: add basic queue operations Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 38/50] net/ntnic: enhance Ethernet device configuration Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 39/50] net/ntnic: add scatter-gather HW deallocation Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 40/50] net/ntnic: add queue setup operations Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 41/50] net/ntnic: add packet handler for virtio queues Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 42/50] net/ntnic: add init for virt queues in the DBS Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 43/50] net/ntnic: add split-queue support Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 44/50] net/ntnic: add functions for availability monitor management Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 45/50] net/ntnic: used writer data handling functions Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 46/50] net/ntnic: add descriptor reader " Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 47/50] net/ntnic: update FPGA registeris related to DBS Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 48/50] net/ntnic: virtqueue setup managed packed-ring was added Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 49/50] net/ntnic: add functions for releasing virt queues Serhii Iliushyk
2024-10-07 19:34 ` [PATCH v2 50/50] net/ntnic: add functions for retrieving and managing packets Serhii Iliushyk
2024-10-09 3:25 ` [PATCH v2 00/50] Provide: flow filter init API, Enable virtual queues, fix ntnic issues for release 24.07 Ferruh Yigit
2024-10-10 11:47 ` Serhii Iliushyk
2024-10-10 12:37 ` Ferruh Yigit
2024-10-10 13:39 ` Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 01/50] net/ntnic: update NT NiC PMD driver with FPGA version Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 02/50] net/ntnic: fix coverity issues: Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 03/50] net/ntnic: update documentation Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 04/50] net/ntnic: remove extra calling of the API for release port Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 05/50] net/ntnic: extend and fix logging implementation Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 06/50] net/ntnic: add flow filter init API Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 07/50] net/ntnic: add flow filter deinitialization API Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 08/50] net/ntnic: add flow backend initialization API Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 09/50] net/ntnic: add flow backend deinitialization API Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 10/50] net/ntnic: add INFO flow module Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 11/50] net/ntnic: add categorizer (CAT) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 12/50] net/ntnic: add key match (KM) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 13/50] net/ntnic: add flow matcher (FLM) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 14/50] net/ntnic: add IP fragmenter (IFR) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 15/50] net/ntnic: add hasher (HSH) " Serhii Iliushyk
2024-11-13 18:09 ` Stephen Hemminger
2024-10-10 14:13 ` [PATCH v3 16/50] net/ntnic: add queue select (QSL) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 17/50] net/ntnic: add slicer (SLC LR) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 18/50] net/ntnic: add packet descriptor builder (PDB) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 19/50] net/ntnic: add header field update (HFU) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 20/50] net/ntnic: add RPP local retransmit (RPP LR) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 21/50] net/ntnic: add copier (Tx CPY) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 22/50] net/ntnic: add checksum update (CSU) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 23/50] net/ntnic: add insert (Tx INS) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 24/50] net/ntnic: add replacer (Tx RPL) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 25/50] net/ntnic: add Tx Packet Editor (TPE) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 26/50] net/ntnic: add base init and deinit of the NT flow API Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 27/50] net/ntnic: add base init and deinit the NT flow backend Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 28/50] net/ntnic: add categorizer (CAT) FPGA module Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 29/50] net/ntnic: add key match (KM) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 30/50] net/ntnic: add flow matcher (FLM) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 31/50] net/ntnic: add hasher (HSH) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 32/50] net/ntnic: add queue select (QSL) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 33/50] net/ntnic: add slicer (SLC LR) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 34/50] net/ntnic: add packet descriptor builder (PDB) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 35/50] net/ntnic: add Tx Packet Editor (TPE) " Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 36/50] net/ntnic: add receive MAC converter (RMC) core module Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 37/50] net/ntnic: add basic queue operations Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 38/50] net/ntnic: enhance Ethernet device configuration Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 39/50] net/ntnic: add scatter-gather HW deallocation Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 40/50] net/ntnic: add queue setup operations Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 41/50] net/ntnic: add packet handler for virtio queues Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 42/50] net/ntnic: add init for virt queues in the DBS Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 43/50] net/ntnic: add split-queue support Serhii Iliushyk
2024-10-10 14:13 ` [PATCH v3 44/50] net/ntnic: add functions for availability monitor management Serhii Iliushyk
2024-10-10 14:14 ` [PATCH v3 45/50] net/ntnic: used writer data handling functions Serhii Iliushyk
2024-10-10 14:14 ` [PATCH v3 46/50] net/ntnic: add descriptor reader " Serhii Iliushyk
2024-10-10 14:14 ` [PATCH v3 47/50] net/ntnic: update FPGA registeris related to DBS Serhii Iliushyk
2024-10-10 14:14 ` [PATCH v3 48/50] net/ntnic: virtqueue setup managed packed-ring was added Serhii Iliushyk
2024-10-10 14:14 ` [PATCH v3 49/50] net/ntnic: add functions for releasing virt queues Serhii Iliushyk
2024-10-10 14:14 ` [PATCH v3 50/50] net/ntnic: add functions for retrieving and managing packets Serhii Iliushyk
2024-10-11 23:22 ` [PATCH v3 00/50] Provide: flow filter init API, Enable virtual queues, fix ntnic issues for release 24.07 Ferruh Yigit
2024-10-06 20:36 ` [PATCH v1 02/50] net/ntnic: fix coverity issues: Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 03/50] net/ntnic: update documentation Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 04/50] net/ntnic: remove extra calling of the API for release port Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 05/50] net/ntnic: extend and fix logging implementation Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 06/50] net/ntnic: add flow filter init API Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 07/50] net/ntnic: add flow filter deinitialization API Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 08/50] net/ntnic: add flow backend initialization API Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 09/50] net/ntnic: add flow backend deinitialization API Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 10/50] net/ntnic: add INFO flow module Serhii Iliushyk
2024-10-06 20:36 ` Serhii Iliushyk [this message]
2024-10-06 20:36 ` [PATCH v1 12/50] net/ntnic: add key match (KM) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 13/50] net/ntnic: add flow matcher (FLM) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 14/50] net/ntnic: add IP fragmenter (IFR) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 15/50] net/ntnic: add hasher (HSH) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 16/50] net/ntnic: add queue select (QSL) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 17/50] net/ntnic: add slicer (SLC LR) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 18/50] net/ntnic: add packet descriptor builder (PDB) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 19/50] net/ntnic: add header field update (HFU) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 20/50] net/ntnic: add RPP local retransmit (RPP LR) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 21/50] net/ntnic: add copier (Tx CPY) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 22/50] net/ntnic: add checksum update (CSU) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 23/50] net/ntnic: add insert (Tx INS) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 24/50] net/ntnic: add replacer (Tx RPL) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 25/50] net/ntnic: add Tx Packet Editor (TPE) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 26/50] net/ntnic: add base init and deinit of the NT flow API Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 27/50] net/ntnic: add base init and deinit the NT flow backend Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 28/50] net/ntnic: add categorizer (CAT) FPGA module Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 29/50] net/ntnic: add key match (KM) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 30/50] net/ntnic: add flow matcher (FLM) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 31/50] net/ntnic: add hasher (HSH) " Serhii Iliushyk
2024-10-06 20:36 ` [PATCH v1 32/50] net/ntnic: add queue select (QSL) " Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 33/50] net/ntnic: add slicer (SLC LR) " Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 34/50] net/ntnic: add packet descriptor builder (PDB) " Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 35/50] net/ntnic: add Tx Packet Editor (TPE) " Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 36/50] net/ntnic: add receive MAC converter (RMC) core module Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 37/50] net/ntnic: add basic queue operations Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 38/50] net/ntnic: enhance Ethernet device configuration Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 39/50] net/ntnic: add scatter-gather HW deallocation Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 40/50] net/ntnic: add queue setup operations Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 41/50] net/ntnic: add packet handler for virtio queues Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 42/50] net/ntnic: add init for virt queues in the DBS Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 43/50] net/ntnic: add split-queue support Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 44/50] net/ntnic: add functions for availability monitor management Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 45/50] net/ntnic: used writer data handling functions Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 46/50] net/ntnic: add descriptor reader " Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 47/50] net/ntnic: update FPGA registeris related to DBS Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 48/50] net/ntnic: virtqueue setup managed packed-ring was added Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 49/50] net/ntnic: add functions for releasing virt queues Serhii Iliushyk
2024-10-06 20:37 ` [PATCH v1 50/50] net/ntnic: add functions for retrieving and managing packets Serhii Iliushyk
2024-10-06 22:27 ` [PATCH v1 00/50] Provide: flow filter init API, Enable virtual queues, fix ntnic issues for release 24.07 Stephen Hemminger
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