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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v4 09/36] KVM: arm64: Extend masking facility to arbitrary registers
Date: Wed,  9 Oct 2024 19:59:52 +0100	[thread overview]
Message-ID: <20241009190019.3222687-10-maz@kernel.org> (raw)
In-Reply-To: <20241009190019.3222687-1-maz@kernel.org>

We currently only use the masking (RES0/RES1) facility for VNCR
registers, as they are memory-based and thus easy to sanitise.

But we could apply the same thing to other registers if we:

- split the sanitisation from __VNCR_START__
- apply the sanitisation when reading from a HW register

This involves a new "marker" in the vcpu_sysreg enum, which
defines the point at which the sanitisation applies (the VNCR
registers being of course after this marker).

Whle we are at it, rename kvm_vcpu_sanitise_vncr_reg() to
kvm_vcpu_apply_reg_masks(), which is vaguely more explicit,
and harden set_sysreg_masks() against setting masks for
random registers...

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/kvm_host.h | 19 +++++++++++++------
 arch/arm64/kvm/nested.c           | 12 ++++++++----
 arch/arm64/kvm/sys_regs.c         |  3 +++
 3 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 1adf68971bb17..7f409dfc5cd4a 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -367,7 +367,7 @@ struct kvm_arch {
 
 	u64 ctr_el0;
 
-	/* Masks for VNCR-baked sysregs */
+	/* Masks for VNCR-backed and general EL2 sysregs */
 	struct kvm_sysreg_masks	*sysreg_masks;
 
 	/*
@@ -401,6 +401,9 @@ struct kvm_vcpu_fault_info {
 	r = __VNCR_START__ + ((VNCR_ ## r) / 8),	\
 	__after_##r = __MAX__(__before_##r - 1, r)
 
+#define MARKER(m)				\
+	m, __after_##m = m - 1
+
 enum vcpu_sysreg {
 	__INVALID_SYSREG__,   /* 0 is reserved as an invalid value */
 	MPIDR_EL1,	/* MultiProcessor Affinity Register */
@@ -487,7 +490,11 @@ enum vcpu_sysreg {
 	CNTHV_CTL_EL2,
 	CNTHV_CVAL_EL2,
 
-	__VNCR_START__,	/* Any VNCR-capable reg goes after this point */
+	/* Anything from this can be RES0/RES1 sanitised */
+	MARKER(__SANITISED_REG_START__),
+
+	/* Any VNCR-capable reg goes after this point */
+	MARKER(__VNCR_START__),
 
 	VNCR(SCTLR_EL1),/* System Control Register */
 	VNCR(ACTLR_EL1),/* Auxiliary Control Register */
@@ -547,7 +554,7 @@ struct kvm_sysreg_masks {
 	struct {
 		u64	res0;
 		u64	res1;
-	} mask[NR_SYS_REGS - __VNCR_START__];
+	} mask[NR_SYS_REGS - __SANITISED_REG_START__];
 };
 
 struct kvm_cpu_context {
@@ -995,13 +1002,13 @@ static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
 
 #define ctxt_sys_reg(c,r)	(*__ctxt_sys_reg(c,r))
 
-u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *, enum vcpu_sysreg);
+u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
 #define __vcpu_sys_reg(v,r)						\
 	(*({								\
 		const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt;	\
 		u64 *__r = __ctxt_sys_reg(ctxt, (r));			\
-		if (vcpu_has_nv((v)) && (r) >= __VNCR_START__)		\
-			*__r = kvm_vcpu_sanitise_vncr_reg((v), (r));	\
+		if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__)	\
+			*__r = kvm_vcpu_apply_reg_masks((v), (r), *__r);\
 		__r;							\
 	}))
 
diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index f9e30dd34c7a1..b20b3bfb9caec 100644
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -908,15 +908,15 @@ static void limit_nv_id_regs(struct kvm *kvm)
 	kvm_set_vm_id_reg(kvm, SYS_ID_AA64DFR0_EL1, val);
 }
 
-u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg sr)
+u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *vcpu,
+			     enum vcpu_sysreg sr, u64 v)
 {
-	u64 v = ctxt_sys_reg(&vcpu->arch.ctxt, sr);
 	struct kvm_sysreg_masks *masks;
 
 	masks = vcpu->kvm->arch.sysreg_masks;
 
 	if (masks) {
-		sr -= __VNCR_START__;
+		sr -= __SANITISED_REG_START__;
 
 		v &= ~masks->mask[sr].res0;
 		v |= masks->mask[sr].res1;
@@ -927,7 +927,11 @@ u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg sr)
 
 static void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1)
 {
-	int i = sr - __VNCR_START__;
+	int i = sr - __SANITISED_REG_START__;
+
+	BUILD_BUG_ON(!__builtin_constant_p(sr));
+	BUILD_BUG_ON(sr < __SANITISED_REG_START__);
+	BUILD_BUG_ON(sr >= NR_SYS_REGS);
 
 	kvm->arch.sysreg_masks->mask[i].res0 = res0;
 	kvm->arch.sysreg_masks->mask[i].res1 = res1;
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 932d2fb7a52a0..d9c20563cae93 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -189,6 +189,9 @@ u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
 
 		/* Get the current version of the EL1 counterpart. */
 		WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val));
+		if (reg >= __SANITISED_REG_START__)
+			val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
+
 		return val;
 	}
 
-- 
2.39.2


  parent reply	other threads:[~2024-10-09 19:00 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-09 18:59 [PATCH v4 00/36] KVM: arm64: Add EL2 support to FEAT_S1PIE/S1POE Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 01/36] arm64: Drop SKL0/SKL1 from TCR2_EL2 Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 02/36] arm64: Remove VNCR definition for PIRE0_EL2 Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 03/36] arm64: Add encoding " Marc Zyngier
2024-10-10 10:46   ` Mark Brown
2024-10-09 18:59 ` [PATCH v4 04/36] KVM: arm64: Drop useless struct s2_mmu in __kvm_at_s1e2() Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 05/36] KVM: arm64: nv: Add missing EL2->EL1 mappings in get_el2_to_el1_mapping() Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 06/36] KVM: arm64: nv: Handle CNTHCTL_EL2 specially Marc Zyngier
2024-10-16  9:37   ` Alexandru Elisei
2024-10-16 11:29     ` Marc Zyngier
2024-10-16 13:19       ` Alexandru Elisei
2024-10-16 13:41         ` Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 07/36] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2024-10-09 19:55   ` Oliver Upton
2024-10-16 13:12   ` Alexandru Elisei
2024-10-16 13:57     ` Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 08/36] KVM: arm64: Correctly access TCR2_EL1, PIR_EL1, PIRE0_EL1 with VHE Marc Zyngier
2024-10-09 18:59 ` Marc Zyngier [this message]
2024-10-09 18:59 ` [PATCH v4 10/36] arm64: Define ID_AA64MMFR1_EL1.HAFDBS advertising FEAT_HAFT Marc Zyngier
2024-10-10 16:20   ` Mark Brown
2024-10-09 18:59 ` [PATCH v4 11/36] KVM: arm64: Add TCR2_EL2 to the sysreg arrays Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 12/36] KVM: arm64: Sanitise TCR2_EL2 Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 13/36] KVM: arm64: Add save/restore for TCR2_EL2 Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 14/36] KVM: arm64: Add PIR{,E0}_EL2 to the sysreg arrays Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 15/36] KVM: arm64: Add save/restore for PIR{,E0}_EL2 Marc Zyngier
2024-10-09 18:59 ` [PATCH v4 16/36] KVM: arm64: Handle PIR{,E0}_EL2 traps Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 17/36] KVM: arm64: Sanitise ID_AA64MMFR3_EL1 Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 18/36] KVM: arm64: Add AT fast-path support for S1PIE Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 19/36] KVM: arm64: Split S1 permission evaluation into direct and hierarchical parts Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 20/36] KVM: arm64: Disable hierarchical permissions when S1PIE is enabled Marc Zyngier
2024-10-10  7:33   ` Oliver Upton
2024-10-10  8:04     ` Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 21/36] KVM: arm64: Implement AT S1PIE support Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 22/36] KVM: arm64: Define helper for EL2 registers with custom visibility Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 23/36] KVM: arm64: Hide TCR2_EL1 from userspace when disabled for guests Marc Zyngier
2024-10-10  7:50   ` Oliver Upton
2024-10-09 19:00 ` [PATCH v4 24/36] KVM: arm64: Hide S1PIE registers " Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 25/36] KVM: arm64: Rely on visibility to let PIR*_ELx/TCR2_ELx UNDEF Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 26/36] arm64: Add encoding for POR_EL2 Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 27/36] KVM: arm64: Add a composite EL2 visibility helper Marc Zyngier
2024-10-10  7:52   ` Oliver Upton
2024-10-09 19:00 ` [PATCH v4 28/36] KVM: arm64: Drop bogus CPTR_EL2.E0POE trap routing Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 29/36] KVM: arm64: Subject S1PIE/S1POE registers to HCR_EL2.{TVM,TRVM} Marc Zyngier
2024-10-10  7:53   ` Oliver Upton
2024-10-09 19:00 ` [PATCH v4 30/36] KVM: arm64: Add basic support for POR_EL2 Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 31/36] KVM: arm64: Add save/retore " Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 32/36] KVM: arm64: Add POE save/restore for AT emulation fast-path Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 33/36] KVM: arm64: Disable hierarchical permissions when POE is enabled Marc Zyngier
2024-10-10  8:08   ` Oliver Upton
2024-10-13 14:27     ` Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 34/36] KVM: arm64: Make PAN conditions part of the S1 walk context Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 35/36] KVM: arm64: Handle stage-1 permission overlays Marc Zyngier
2024-10-09 19:00 ` [PATCH v4 36/36] KVM: arm64: Handle WXN attribute Marc Zyngier

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