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[209.91.167.254]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cbe862fe87sm7116246d6.106.2024.10.10.10.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 10:32:23 -0700 (PDT) Date: Thu, 10 Oct 2024 13:32:21 -0400 From: Trevor Woerner To: Dragan Simic Cc: linux-rockchip@lists.infradead.org, heiko@sntech.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] arm64: dts: rockchip: Prevent thermal runaways in RK3308 SoC dtsi Message-ID: <20241010173154.GA32479@localhost> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241010_183228_668778_A579031C X-CRM114-Status: GOOD ( 17.22 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On Thu 2024-10-10 @ 12:19:41 PM, Dragan Simic wrote: > Until the TSADC, thermal zones, thermal trips and cooling maps are defined > in the RK3308 SoC dtsi, none of the CPU OPPs except the slowest one may be > enabled under any circumstances. Allowing the DVFS to scale the CPU cores > up without even just the critical CPU thermal trip in place can rather easily > result in thermal runaways and damaged SoCs, which is bad. > > Thus, leave only the lowest available CPU OPP enabled for now. > It builds, it runs, it's been running on one of my rock-pi-s boards for ~3h now. I can read my spi, i2c, and w1 sensors, so no issues for me. # cat /sys/bus/cpu/devices/cpu*/cpufreq/stats/time_in_state 408000 1168942 408000 1168942 408000 1168942 408000 1168942 Tested-by: Trevor Woerner > Fixes: 6913c45239fd ("arm64: dts: rockchip: Add core dts for RK3308 SOC") > Cc: stable@vger.kernel.org > Signed-off-by: Dragan Simic > --- > arch/arm64/boot/dts/rockchip/rk3308.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi > index 31c25de2d689..a7698e1f6b9e 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi > @@ -120,16 +120,19 @@ opp-600000000 { > opp-hz = /bits/ 64 <600000000>; > opp-microvolt = <950000 950000 1340000>; > clock-latency-ns = <40000>; > + status = "disabled"; > }; > opp-816000000 { > opp-hz = /bits/ 64 <816000000>; > opp-microvolt = <1025000 1025000 1340000>; > clock-latency-ns = <40000>; > + status = "disabled"; > }; > opp-1008000000 { > opp-hz = /bits/ 64 <1008000000>; > opp-microvolt = <1125000 1125000 1340000>; > clock-latency-ns = <40000>; > + status = "disabled"; > }; > }; > > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qv1-f48.google.com (mail-qv1-f48.google.com [209.85.219.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50E5D18950A; Thu, 10 Oct 2024 17:32:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.48 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728581546; cv=none; b=D4dRXaJBK/mA18mHFD2ZTajOOFFrFAwFRvxhz0Dxp+shSGz1xZ0E4YUnE1QuqKC5TyAQ9tBdCmKffX96bwj2Z5ZsldnJ4XLGYblpULTxSD7R5VuoPOMhJyiKSWJDNWz7Q/ZvSILWgUsw8nTywITwzf5b+VQhLoBORbOhSQvG+QY= ARC-Message-Signature:i=1; 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[209.91.167.254]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cbe862fe87sm7116246d6.106.2024.10.10.10.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 10:32:23 -0700 (PDT) Date: Thu, 10 Oct 2024 13:32:21 -0400 From: Trevor Woerner To: Dragan Simic Cc: linux-rockchip@lists.infradead.org, heiko@sntech.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] arm64: dts: rockchip: Prevent thermal runaways in RK3308 SoC dtsi Message-ID: <20241010173154.GA32479@localhost> References: Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) On Thu 2024-10-10 @ 12:19:41 PM, Dragan Simic wrote: > Until the TSADC, thermal zones, thermal trips and cooling maps are defined > in the RK3308 SoC dtsi, none of the CPU OPPs except the slowest one may be > enabled under any circumstances. Allowing the DVFS to scale the CPU cores > up without even just the critical CPU thermal trip in place can rather easily > result in thermal runaways and damaged SoCs, which is bad. > > Thus, leave only the lowest available CPU OPP enabled for now. > It builds, it runs, it's been running on one of my rock-pi-s boards for ~3h now. I can read my spi, i2c, and w1 sensors, so no issues for me. # cat /sys/bus/cpu/devices/cpu*/cpufreq/stats/time_in_state 408000 1168942 408000 1168942 408000 1168942 408000 1168942 Tested-by: Trevor Woerner > Fixes: 6913c45239fd ("arm64: dts: rockchip: Add core dts for RK3308 SOC") > Cc: stable@vger.kernel.org > Signed-off-by: Dragan Simic > --- > arch/arm64/boot/dts/rockchip/rk3308.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi > index 31c25de2d689..a7698e1f6b9e 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi > @@ -120,16 +120,19 @@ opp-600000000 { > opp-hz = /bits/ 64 <600000000>; > opp-microvolt = <950000 950000 1340000>; > clock-latency-ns = <40000>; > + status = "disabled"; > }; > opp-816000000 { > opp-hz = /bits/ 64 <816000000>; > opp-microvolt = <1025000 1025000 1340000>; > clock-latency-ns = <40000>; > + status = "disabled"; > }; > opp-1008000000 { > opp-hz = /bits/ 64 <1008000000>; > opp-microvolt = <1125000 1125000 1340000>; > clock-latency-ns = <40000>; > + status = "disabled"; > }; > }; > >