From: Minda Chen <minda.chen@starfivetech.com>
To: Marek Vasut <marex@denx.de>, Tom Rini <trini@konsulko.com>,
Roger Quadros <rogerq@kernel.org>, Rick Chen <rick@andestech.com>,
Leo <ycliang@andestech.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Alexey Romanov <avromanov@salutedevices.com>,
Sumit Garg <sumit.garg@linaro.org>,
Mark Kettenis <kettenis@openbsd.org>, Nishanth Menon <nm@ti.com>
Cc: u-boot@lists.denx.de, Heinrich Schuchardt <xypron.glpk@gmx.de>,
Simon Glass <sjg@chromium.org>, E Shattow <lucent@gmail.com>,
Minda Chen <minda.chen@starfivetech.com>
Subject: [PATCH v5 2/8] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
Date: Sat, 12 Oct 2024 11:13:22 +0800 [thread overview]
Message-ID: <20241012031328.4268-3-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20241012031328.4268-1-minda.chen@starfivetech.com>
Add Starfive JH7110 USB 2.0 PHY driver, which is generic
PHY driver.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/starfive/Kconfig | 14 ++
drivers/phy/starfive/Makefile | 6 +
drivers/phy/starfive/phy-jh7110-usb-syscon.h | 9 ++
drivers/phy/starfive/phy-jh7110-usb2.c | 162 +++++++++++++++++++
6 files changed, 193 insertions(+)
create mode 100644 drivers/phy/starfive/Kconfig
create mode 100644 drivers/phy/starfive/Makefile
create mode 100644 drivers/phy/starfive/phy-jh7110-usb-syscon.h
create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e12347e8a03..f940648fe58 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -309,5 +309,6 @@ source "drivers/phy/cadence/Kconfig"
source "drivers/phy/ti/Kconfig"
source "drivers/phy/qcom/Kconfig"
source "drivers/phy/renesas/Kconfig"
+source "drivers/phy/starfive/Kconfig"
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 7a2b764492b..6ac867350cb 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -44,3 +44,4 @@ obj-y += cadence/
obj-y += ti/
obj-y += qcom/
obj-y += renesas/
+obj-y += starfive/
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
new file mode 100644
index 00000000000..a7cf0a55dff
--- /dev/null
+++ b/drivers/phy/starfive/Kconfig
@@ -0,0 +1,14 @@
+#
+# PHY drivers for Starfive platforms
+#
+
+menu "Starfive PHY driver"
+
+config PHY_STARFIVE_JH7110_USB2
+ bool "Starfive JH7110 USB 2.0 PHY driver"
+ depends on PHY
+ help
+ Enable this to support the Starfive JH7110 USB 2.0 PHY.
+ Generic PHY driver JH7110 USB 2.0.
+
+endmenu
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
new file mode 100644
index 00000000000..a405a75e34c
--- /dev/null
+++ b/drivers/phy/starfive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Starfive
+#
+
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-usb-syscon.h b/drivers/phy/starfive/phy-jh7110-usb-syscon.h
new file mode 100644
index 00000000000..0eb66f0d859
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb-syscon.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef PHY_JH7110_USB_SYSCON_H_
+#define PHY_JH7110_USB_SYSCON_H_
+
+#define SYSCON_USB_PDRSTN_REG_OFFSET 0x18
+#define USB_PDRSTN_SPLIT_BIT 17
+
+#endif
diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c
new file mode 100644
index 00000000000..1a28381e0df
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb2.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <soc.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#include "phy-jh7110-usb-syscon.h"
+
+#define USB_LS_KEEPALIVE_OFF 0x4
+#define USB_LS_KEEPALIVE_ENABLE BIT(4)
+#define USB_PHY_CLK_RATE 125000000
+
+struct jh7110_usb2_phy {
+ struct phy *phy;
+ struct regmap *sys_syscon;
+ void __iomem *regs;
+ struct clk *usb_125m_clk;
+ struct clk *app_125m;
+ struct regmap_field *usb_split;
+ enum phy_mode mode;
+};
+
+static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set)
+{
+ /* Host mode enable the LS speed keep-alive signal */
+ clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+ USB_LS_KEEPALIVE_ENABLE,
+ set ? USB_LS_KEEPALIVE_ENABLE : 0);
+}
+
+static int usb2_phy_set_mode(struct phy *phy,
+ enum phy_mode mode, int submode)
+{
+ struct udevice *dev = phy->dev;
+ struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev);
+
+ if (mode == usb2_phy->mode)
+ return 0;
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ dev_dbg(dev, "Changing PHY to %d\n", mode);
+ usb2_phy->mode = mode;
+ usb2_set_ls_keepalive(usb2_phy, (mode != PHY_MODE_USB_DEVICE));
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* set default split usb 2.0 only mode */
+ regmap_field_write(usb2_phy->usb_split, true);
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_set_rate(usb2_phy->usb_125m_clk, USB_PHY_CLK_RATE);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set 125m clock\n");
+ return ret;
+ }
+
+ return clk_prepare_enable(usb2_phy->app_125m);
+}
+
+static int jh7110_usb2_phy_exit(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev);
+
+ clk_disable_unprepare(usb2_phy->app_125m);
+
+ return 0;
+}
+
+struct phy_ops jh7110_usb2_phy_ops = {
+ .init = jh7110_usb2_phy_init,
+ .exit = jh7110_usb2_phy_exit,
+ .set_mode = usb2_phy_set_mode,
+};
+
+int jh7110_usb2_phy_probe(struct udevice *dev)
+{
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+ ofnode node;
+ struct reg_field usb_split;
+ int ret;
+
+ phy->regs = dev_read_addr_ptr(dev);
+ if (!phy->regs)
+ return -EINVAL;
+
+ node = ofnode_by_compatible(ofnode_null(), "starfive,jh7110-sys-syscon");
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "Can't get syscon dev node\n");
+ return -ENODEV;
+ }
+
+ phy->sys_syscon = syscon_node_to_regmap(node);
+ if (IS_ERR(phy->sys_syscon)) {
+ dev_err(dev, "Can't get syscon regmap: %d\n", ret);
+ return PTR_ERR(phy->sys_syscon);
+ }
+
+ usb_split.reg = SYSCON_USB_PDRSTN_REG_OFFSET;
+ usb_split.lsb = USB_PDRSTN_SPLIT_BIT;
+ usb_split.msb = USB_PDRSTN_SPLIT_BIT;
+ phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split);
+ if (IS_ERR(phy->usb_split)) {
+ dev_err(dev, "USB split field init failed\n");
+ return PTR_ERR(phy->usb_split);
+ }
+
+ phy->usb_125m_clk = devm_clk_get(dev, "125m");
+ if (IS_ERR(phy->usb_125m_clk)) {
+ dev_err(dev, "Failed to get 125m clock\n");
+ return PTR_ERR(phy->usb_125m_clk);
+ }
+
+ phy->app_125m = devm_clk_get(dev, "app_125m");
+ if (IS_ERR(phy->app_125m)) {
+ dev_err(dev, "Failed to get app 125m clock\n");
+ return PTR_ERR(phy->app_125m);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_usb2_phy[] = {
+ { .compatible = "starfive,jh7110-usb-phy"},
+ {},
+};
+
+U_BOOT_DRIVER(jh7110_usb2_phy) = {
+ .name = "jh7110_usb2_phy",
+ .id = UCLASS_PHY,
+ .of_match = jh7110_usb2_phy,
+ .probe = jh7110_usb2_phy_probe,
+ .ops = &jh7110_usb2_phy_ops,
+ .priv_auto = sizeof(struct jh7110_usb2_phy),
+};
--
2.17.1
next prev parent reply other threads:[~2024-10-12 3:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-12 3:13 [PATCH v5 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
2024-10-12 3:13 ` [PATCH v5 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() Minda Chen
2024-10-12 3:13 ` Minda Chen [this message]
2024-10-12 3:13 ` [PATCH v5 3/8] phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver Minda Chen
2024-10-12 3:13 ` [PATCH v5 4/8] usb: cdns: starfive: Add cdns USB driver Minda Chen
2024-10-12 3:34 ` Marek Vasut
2024-12-16 7:37 ` E Shattow
2024-12-19 8:28 ` 回复: " Minda Chen
2024-10-12 3:13 ` [PATCH v5 5/8] spl: starfive: visionfive2: Disable USB overcurrent pin by default Minda Chen
2024-10-12 3:13 ` [PATCH v5 6/8] configs: starfive: Add visionfive2 cadence USB configuration Minda Chen
2024-10-12 3:13 ` [PATCH v5 7/8] dts: starfive: Add JH7110 Cadence USB dts node Minda Chen
2024-12-16 7:31 ` E Shattow
2024-10-12 3:13 ` [PATCH v5 8/8] MAINTAINERS: Update Starfive visionfive2 maintain files Minda Chen
2024-11-22 8:16 ` [PATCH v5 0/8] Add Starfive JH7110 Cadence USB driver E Shattow
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