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[185.176.79.56]) by mx.google.com with ESMTPS id ffacd0b85a97d-37d7fcca23esi2699997f8f.700.2024.10.17.02.06.07 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Oct 2024 02:06:07 -0700 (PDT) Received-SPF: pass (google.com: domain of jonathan.cameron@huawei.com designates 185.176.79.56 as permitted sender) client-ip=185.176.79.56; Authentication-Results: mx.google.com; spf=pass (google.com: domain of jonathan.cameron@huawei.com designates 185.176.79.56 as permitted sender) smtp.mailfrom=jonathan.cameron@huawei.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4XThkZ5DQTz6JBHx; Thu, 17 Oct 2024 17:05:26 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 899DE140D1A; Thu, 17 Oct 2024 17:06:06 +0800 (CST) Received: from localhost (10.126.174.164) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Thu, 17 Oct 2024 11:06:04 +0200 Date: Thu, 17 Oct 2024 10:06:03 +0100 From: Jonathan Cameron To: Zhao Liu CC: "Daniel P .\" =?ISO-8859-1?Q?Berrang=E9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , Philippe =?ISO-8859-1?Q?Ma?= =?ISO-8859-1?Q?thieu-Daud=E9?= , Yanan Wang , Michael S.Tsirkin , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , Alex =?ISO-8859-1?Q?Benn=E9e?= , Peter Maydell , Sia Jee Heng , Alireza Sanaee , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi "@domain.invalid Subject: Re: [PATCH v3 7/7] i386/cpu: add has_caches flag to check smp_cache configuration Message-ID: <20241017100603.00003a57@Huawei.com> In-Reply-To: <20241012104429.1048908-8-zhao1.liu@intel.com> References: <20241012104429.1048908-1-zhao1.liu@intel.com> <20241012104429.1048908-8-zhao1.liu@intel.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.126.174.164] X-ClientProxiedBy: lhrpeml500004.china.huawei.com (7.191.163.9) To frapeml500008.china.huawei.com (7.182.85.71) X-TUID: sF2lS+j3hqQB On Sat, 12 Oct 2024 18:44:29 +0800 Zhao Liu wrote: > From: Alireza Sanaee > > Add has_caches flag to SMPCompatProps, which helps in avoiding > extra checks for every single layer of caches in x86 (and ARM in > future). > > Signed-off-by: Alireza Sanaee > Signed-off-by: Zhao Liu LGTM Reviewed-by: Jonathan Cameron > --- > Note: Picked from Alireza's series with the changes: > * Moved the flag to SMPCompatProps with a new name "has_caches". > This way, it remains consistent with the function and style of > "has_clusters" in SMPCompatProps. > * Dropped my previous TODO with the new flag. > --- > Changes since Patch v2: > * Picked a new patch frome Alireza's ARM smp-cache series. > --- > hw/core/machine-smp.c | 2 ++ > include/hw/boards.h | 3 +++ > target/i386/cpu.c | 9 ++++----- > 3 files changed, 9 insertions(+), 5 deletions(-) > > diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c > index f3edbded2e7b..16e456678cb6 100644 > --- a/hw/core/machine-smp.c > +++ b/hw/core/machine-smp.c > @@ -367,6 +367,8 @@ bool machine_parse_smp_cache(MachineState *ms, > return false; > } > > + mc->smp_props.has_caches = true; > + > return true; > } > > diff --git a/include/hw/boards.h b/include/hw/boards.h > index e4a1035e3fa1..af62b09c89d1 100644 > --- a/include/hw/boards.h > +++ b/include/hw/boards.h > @@ -153,6 +153,8 @@ typedef struct { > * @modules_supported - whether modules are supported by the machine > * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are > * supported by the machine > + * @has_caches - whether cache properties are explicitly specified in the > + * user provided smp-cache configuration > */ > typedef struct { > bool prefer_sockets; > @@ -163,6 +165,7 @@ typedef struct { > bool drawers_supported; > bool modules_supported; > bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; > + bool has_caches; > } SMPCompatProps; > > /** > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index c8a04faf3764..6f711e98b527 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -7853,12 +7853,11 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) > > #ifndef CONFIG_USER_ONLY > MachineState *ms = MACHINE(qdev_get_machine()); > + MachineClass *mc = MACHINE_GET_CLASS(ms); > > - /* > - * TODO: Add a SMPCompatProps.has_caches flag to avoid useless Updates > - * if user didn't set smp_cache. > - */ > - x86_cpu_update_smp_cache_topo(ms, cpu); > + if (mc->smp_props.has_caches) { > + x86_cpu_update_smp_cache_topo(ms, cpu); > + } > > qemu_register_reset(x86_cpu_machine_reset_cb, cpu); >