From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Maciej W. Rozycki" <macro@orcam.me.uk>,
"Lukas Wunner" <lukas@wunner.de>,
"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
linux-pm@vger.kernel.org,
"Smita Koralahalli" <Smita.KoralahalliChannabasappa@amd.com>,
linux-kernel@vger.kernel.org,
"Daniel Lezcano" <daniel.lezcano@linaro.org>,
"Amit Kucheria" <amitk@kernel.org>,
"Zhang Rui" <rui.zhang@intel.com>,
"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>
Subject: Re: [PATCH v8 6/8] PCI/bwctrl: Add API to set PCIe Link Speed
Date: Thu, 17 Oct 2024 12:02:11 +0100 [thread overview]
Message-ID: <20241017120211.00005b1e@Huawei.com> (raw)
In-Reply-To: <20241009095223.7093-7-ilpo.jarvinen@linux.intel.com>
On Wed, 9 Oct 2024 12:52:21 +0300
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> wrote:
> Currently, PCIe Link Speeds are adjusted by custom code rather than in
> a common function provided in PCI core. PCIe bandwidth controller
> (bwctrl) introduces an in-kernel API to set PCIe Link Speed.
>
> Convert Target Speed quirk to use the new API. The Target Speed quirk
> runs very early when bwctrl is not yet probed for a Port and can also
> run later when bwctrl is already setup for the Port, which requires the
> per port mutex (set_speed_mutex) to be only taken if the bwctrl setup
> is already complete.
>
> The new API is also intended to be used in an upcoming commit that adds
> a thermal cooling device to throttle PCIe bandwidth when thermal
> thresholds are reached.
>
> The PCIe bandwidth control procedure is as follows. The highest speed
> supported by the Port and the PCIe device which is not higher than the
> requested speed is selected and written into the Target Link Speed in
> the Link Control 2 Register. Then bandwidth controller retrains the
> PCIe Link.
>
> Bandwidth Notifications enable the cur_bus_speed in the struct pci_bus
> to keep track PCIe Link Speed changes. While Bandwidth Notifications
> should also be generated when bandwidth controller alters the PCIe Link
> Speed, a few platforms do not deliver LMBS interrupt after Link
> Training as expected. Thus, after changing the Link Speed, bandwidth
> controller makes additional read for the Link Status Register to ensure
> cur_bus_speed is consistent with the new PCIe Link Speed.
>
> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Trivial stuff inline. The mutex_destroy discussion is a just a consistency
thing given that call is rarely bothered with but here it might help with
debug.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Jonathan
> ---
> drivers/pci/pci.h | 20 +++++
> drivers/pci/pcie/bwctrl.c | 161 +++++++++++++++++++++++++++++++++++++-
> drivers/pci/quirks.c | 17 +---
> include/linux/pci.h | 10 +++
> 4 files changed, 193 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
> index 1b11b5da79d4..1d3680ea8e06 100644
> --- a/drivers/pci/pcie/bwctrl.c
> +++ b/drivers/pci/pcie/bwctrl.c
> @@ -7,6 +7,11 @@
> static void pcie_bwnotif_enable(struct pcie_device *srv)
> {
> struct pcie_bwctrl_data *data = get_service_data(srv);
> @@ -135,6 +288,7 @@ static int pcie_bwnotif_probe(struct pcie_device *srv)
> if (!data)
> return -ENOMEM;
>
> + mutex_init(&data->set_speed_mutex);
> set_service_data(srv, data);
>
> ret = request_threaded_irq(srv->irq, NULL, pcie_bwnotif_irq_thread,
> @@ -142,8 +296,10 @@ static int pcie_bwnotif_probe(struct pcie_device *srv)
> if (ret)
> return ret;
>
> - port->link_bwctrl = no_free_ptr(data);
> - pcie_bwnotif_enable(srv);
> + scoped_guard(rwsem_write, &pcie_bwctrl_remove_rwsem) {
Calling it remove_rwsem and using it to protect against not yet
present seems odd. Maybe rename, pcie_bwctrl_bound_rswem or something like that?
> + port->link_bwctrl = no_free_ptr(data);
> + pcie_bwnotif_enable(srv);
> + }
>
> pci_dbg(port, "enabled with IRQ %d\n", srv->irq);
>
> @@ -159,6 +315,7 @@ static void pcie_bwnotif_remove(struct pcie_device *srv)
> srv->port->link_bwctrl = NULL;
>
> free_irq(srv->irq, srv);
> + mutex_destroy(&data->set_speed_mutex);
Probably not worth doing. Also you don't do error handling for this above.
Ideal is use devm_ for data and then devm_mutex_init()
> kfree(data);
> }
>
next prev parent reply other threads:[~2024-10-17 11:02 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-09 9:52 [PATCH v8 0/8] PCI: Add PCIe bandwidth controller Ilpo Järvinen
2024-10-09 9:52 ` [PATCH v8 1/8] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2024-10-17 10:12 ` Jonathan Cameron
2024-10-17 10:30 ` Ilpo Järvinen
2024-10-09 9:52 ` [PATCH v8 2/8] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2024-10-17 10:25 ` Jonathan Cameron
2024-10-09 9:52 ` [PATCH v8 3/8] PCI: Refactor pcie_update_link_speed() Ilpo Järvinen
2024-10-17 10:26 ` Jonathan Cameron
2024-10-09 9:52 ` [PATCH v8 4/8] PCI/quirks: Abstract LBMS seen check into own function Ilpo Järvinen
2024-10-17 10:29 ` Jonathan Cameron
2024-10-09 9:52 ` [PATCH v8 5/8] PCI/bwctrl: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2024-10-17 10:48 ` Jonathan Cameron
2024-10-09 9:52 ` [PATCH v8 6/8] PCI/bwctrl: Add API to set PCIe Link Speed Ilpo Järvinen
2024-10-17 11:02 ` Jonathan Cameron [this message]
2024-10-17 13:16 ` Ilpo Järvinen
2024-10-09 9:52 ` [PATCH v8 7/8] thermal: Add PCIe cooling driver Ilpo Järvinen
2024-10-17 11:04 ` Jonathan Cameron
2024-10-17 12:16 ` Ilpo Järvinen
2024-10-17 12:58 ` Rafael J. Wysocki
2024-10-17 13:02 ` Ilpo Järvinen
2024-10-17 13:28 ` Jonathan Cameron
2024-10-09 9:52 ` [PATCH v8 8/8] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
2024-10-17 11:08 ` Jonathan Cameron
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