From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anup Patel Date: Mon, 21 Oct 2024 01:17:21 +0530 Subject: [PATCH v2 00/13] Accelerate KVM RISC-V when running as a guest Message-ID: <20241020194734.58686-1-apatel@ventanamicro.com> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit The KVM RISC-V hypervisor might be running as a guest under some other host hypervisor in which case the complete H-extension functionality will be trap-n-emulated by the host hypervisor. In this case, the KVM RISC-V performance can be accelerated using the SBI nested acceleration (NACL) extension if the host hypervisor provides it. These series extends KVM RISC-V to use SBI NACL extension whenever underlying SBI implementation (aka host hypervisor) provides it. These patches can also be found in the riscv_sbi_nested_v2 branch at: https://github.com/avpatel/linux.git To test these patches, run KVM RISC-V as Guest under latest Xvisor found at: https://github.com/xvisor/xvisor.git For the steps to test on Xvisor, refer the Xvisor documentation /docs/riscv/riscv64-qemu.txt with two small changes: 1) In step#11, make sure compressed kvm.ko, guest kernel image, and kvmtool are present in the rootfs.img 2) In step#14, make sure AIA is available to Xvisor by using "virt,aia=aplic-imsic" as the QEMU machine name. Changes since v1: - Dropped nacl_shmem_fast() macro from PATCH8 - Added comments in PATCH8 about which back-to-back ncsr_xyz() macros are sub-optimal - Moved nacl_scratch_xyz() macros to PATCH8 Anup Patel (13): RISC-V: KVM: Order the object files alphabetically RISC-V: KVM: Save/restore HSTATUS in C source RISC-V: KVM: Save/restore SCOUNTEREN in C source RISC-V: KVM: Break down the __kvm_riscv_switch_to() into macros RISC-V: KVM: Replace aia_set_hvictl() with aia_hvictl_value() RISC-V: KVM: Don't setup SGEI for zero guest external interrupts RISC-V: Add defines for the SBI nested acceleration extension RISC-V: KVM: Add common nested acceleration support RISC-V: KVM: Use nacl_csr_xyz() for accessing H-extension CSRs RISC-V: KVM: Use nacl_csr_xyz() for accessing AIA CSRs RISC-V: KVM: Use SBI sync SRET call when available RISC-V: KVM: Save trap CSRs in kvm_riscv_vcpu_enter_exit() RISC-V: KVM: Use NACL HFENCEs for KVM request based HFENCEs arch/riscv/include/asm/kvm_nacl.h | 245 ++++++++++++++++++++++++++++++ arch/riscv/include/asm/sbi.h | 120 +++++++++++++++ arch/riscv/kvm/Makefile | 27 ++-- arch/riscv/kvm/aia.c | 114 +++++++++----- arch/riscv/kvm/main.c | 51 ++++++- arch/riscv/kvm/mmu.c | 4 +- arch/riscv/kvm/nacl.c | 152 ++++++++++++++++++ arch/riscv/kvm/tlb.c | 57 ++++--- arch/riscv/kvm/vcpu.c | 184 ++++++++++++++++------ arch/riscv/kvm/vcpu_switch.S | 137 +++++++++++------ arch/riscv/kvm/vcpu_timer.c | 28 ++-- 11 files changed, 941 insertions(+), 178 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_nacl.h create mode 100644 arch/riscv/kvm/nacl.c -- 2.43.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07B5F11C83 for ; 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Sun, 20 Oct 2024 12:47:44 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([50.238.223.131]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e5ad365d4dsm1933188a91.14.2024.10.20.12.47.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:47:43 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 00/13] Accelerate KVM RISC-V when running as a guest Date: Mon, 21 Oct 2024 01:17:21 +0530 Message-ID: <20241020194734.58686-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The KVM RISC-V hypervisor might be running as a guest under some other host hypervisor in which case the complete H-extension functionality will be trap-n-emulated by the host hypervisor. In this case, the KVM RISC-V performance can be accelerated using the SBI nested acceleration (NACL) extension if the host hypervisor provides it. These series extends KVM RISC-V to use SBI NACL extension whenever underlying SBI implementation (aka host hypervisor) provides it. These patches can also be found in the riscv_sbi_nested_v2 branch at: https://github.com/avpatel/linux.git To test these patches, run KVM RISC-V as Guest under latest Xvisor found at: https://github.com/xvisor/xvisor.git For the steps to test on Xvisor, refer the Xvisor documentation /docs/riscv/riscv64-qemu.txt with two small changes: 1) In step#11, make sure compressed kvm.ko, guest kernel image, and kvmtool are present in the rootfs.img 2) In step#14, make sure AIA is available to Xvisor by using "virt,aia=aplic-imsic" as the QEMU machine name. Changes since v1: - Dropped nacl_shmem_fast() macro from PATCH8 - Added comments in PATCH8 about which back-to-back ncsr_xyz() macros are sub-optimal - Moved nacl_scratch_xyz() macros to PATCH8 Anup Patel (13): RISC-V: KVM: Order the object files alphabetically RISC-V: KVM: Save/restore HSTATUS in C source RISC-V: KVM: Save/restore SCOUNTEREN in C source RISC-V: KVM: Break down the __kvm_riscv_switch_to() into macros RISC-V: KVM: Replace aia_set_hvictl() with aia_hvictl_value() RISC-V: KVM: Don't setup SGEI for zero guest external interrupts RISC-V: Add defines for the SBI nested acceleration extension RISC-V: KVM: Add common nested acceleration support RISC-V: KVM: Use nacl_csr_xyz() for accessing H-extension CSRs RISC-V: KVM: Use nacl_csr_xyz() for accessing AIA CSRs RISC-V: KVM: Use SBI sync SRET call when available RISC-V: KVM: Save trap CSRs in kvm_riscv_vcpu_enter_exit() RISC-V: KVM: Use NACL HFENCEs for KVM request based HFENCEs arch/riscv/include/asm/kvm_nacl.h | 245 ++++++++++++++++++++++++++++++ arch/riscv/include/asm/sbi.h | 120 +++++++++++++++ arch/riscv/kvm/Makefile | 27 ++-- arch/riscv/kvm/aia.c | 114 +++++++++----- arch/riscv/kvm/main.c | 51 ++++++- arch/riscv/kvm/mmu.c | 4 +- arch/riscv/kvm/nacl.c | 152 ++++++++++++++++++ arch/riscv/kvm/tlb.c | 57 ++++--- arch/riscv/kvm/vcpu.c | 184 ++++++++++++++++------ arch/riscv/kvm/vcpu_switch.S | 137 +++++++++++------ arch/riscv/kvm/vcpu_timer.c | 28 ++-- 11 files changed, 941 insertions(+), 178 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_nacl.h create mode 100644 arch/riscv/kvm/nacl.c -- 2.43.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E92E2D3C92D for ; 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Sun, 20 Oct 2024 12:47:44 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([50.238.223.131]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e5ad365d4dsm1933188a91.14.2024.10.20.12.47.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 12:47:43 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 00/13] Accelerate KVM RISC-V when running as a guest Date: Mon, 21 Oct 2024 01:17:21 +0530 Message-ID: <20241020194734.58686-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241020_124745_725716_6850891D X-CRM114-Status: GOOD ( 11.47 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The KVM RISC-V hypervisor might be running as a guest under some other host hypervisor in which case the complete H-extension functionality will be trap-n-emulated by the host hypervisor. In this case, the KVM RISC-V performance can be accelerated using the SBI nested acceleration (NACL) extension if the host hypervisor provides it. These series extends KVM RISC-V to use SBI NACL extension whenever underlying SBI implementation (aka host hypervisor) provides it. These patches can also be found in the riscv_sbi_nested_v2 branch at: https://github.com/avpatel/linux.git To test these patches, run KVM RISC-V as Guest under latest Xvisor found at: https://github.com/xvisor/xvisor.git For the steps to test on Xvisor, refer the Xvisor documentation /docs/riscv/riscv64-qemu.txt with two small changes: 1) In step#11, make sure compressed kvm.ko, guest kernel image, and kvmtool are present in the rootfs.img 2) In step#14, make sure AIA is available to Xvisor by using "virt,aia=aplic-imsic" as the QEMU machine name. Changes since v1: - Dropped nacl_shmem_fast() macro from PATCH8 - Added comments in PATCH8 about which back-to-back ncsr_xyz() macros are sub-optimal - Moved nacl_scratch_xyz() macros to PATCH8 Anup Patel (13): RISC-V: KVM: Order the object files alphabetically RISC-V: KVM: Save/restore HSTATUS in C source RISC-V: KVM: Save/restore SCOUNTEREN in C source RISC-V: KVM: Break down the __kvm_riscv_switch_to() into macros RISC-V: KVM: Replace aia_set_hvictl() with aia_hvictl_value() RISC-V: KVM: Don't setup SGEI for zero guest external interrupts RISC-V: Add defines for the SBI nested acceleration extension RISC-V: KVM: Add common nested acceleration support RISC-V: KVM: Use nacl_csr_xyz() for accessing H-extension CSRs RISC-V: KVM: Use nacl_csr_xyz() for accessing AIA CSRs RISC-V: KVM: Use SBI sync SRET call when available RISC-V: KVM: Save trap CSRs in kvm_riscv_vcpu_enter_exit() RISC-V: KVM: Use NACL HFENCEs for KVM request based HFENCEs arch/riscv/include/asm/kvm_nacl.h | 245 ++++++++++++++++++++++++++++++ arch/riscv/include/asm/sbi.h | 120 +++++++++++++++ arch/riscv/kvm/Makefile | 27 ++-- arch/riscv/kvm/aia.c | 114 +++++++++----- arch/riscv/kvm/main.c | 51 ++++++- arch/riscv/kvm/mmu.c | 4 +- arch/riscv/kvm/nacl.c | 152 ++++++++++++++++++ arch/riscv/kvm/tlb.c | 57 ++++--- arch/riscv/kvm/vcpu.c | 184 ++++++++++++++++------ arch/riscv/kvm/vcpu_switch.S | 137 +++++++++++------ arch/riscv/kvm/vcpu_timer.c | 28 ++-- 11 files changed, 941 insertions(+), 178 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_nacl.h create mode 100644 arch/riscv/kvm/nacl.c -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv