From: Christoph Hellwig <hch@lst.de>
To: Ming Lei <ming.lei@redhat.com>
Cc: Christoph Hellwig <hch@lst.de>,
Catalin Marinas <catalin.marinas@arm.com>,
linux-block@vger.kernel.org, Keith Busch <kbusch@kernel.org>,
Jens Axboe <axboe@kernel.dk>, Robin Murphy <robin.murphy@arm.com>
Subject: Re: [Regression] b1a000d3b8ec ("block: relax direct io memory alignment")
Date: Wed, 23 Oct 2024 14:23:39 +0200 [thread overview]
Message-ID: <20241023122338.GD28777@lst.de> (raw)
In-Reply-To: <ZxiwaupwAkf1u8VE@fedora>
On Wed, Oct 23, 2024 at 04:14:34PM +0800, Ming Lei wrote:
> On Wed, Oct 23, 2024 at 08:12:33AM +0200, Christoph Hellwig wrote:
> > On Tue, Oct 22, 2024 at 11:24:31AM +0100, Catalin Marinas wrote:
> > > > > We should not allow smaller than cache line alignment on architectures
> > > > > that are not cache coherent indeed.
> > >
> > > Even on architectures that are not fully coherent, the coherency is a
> > > property of the device. You may need to somehow pass this information in
> > > struct queue_limits if you want it to be optimal.
> >
> > Well, devices set the queue limits. So this would be a fix in the
> > drivers that set the queue limits. SCSI already does this in the
> > midlayer code,
>
> I guess it isn't true:
>
> [linux]# cat /sys/block/sda/queue/dma_alignment
Is that a SCSI HBA that is on a not DMA coherent bus? If not that
is expected.
prev parent reply other threads:[~2024-10-23 12:23 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 16:40 [Regression] b1a000d3b8ec ("block: relax direct io memory alignment") Ming Lei
2024-10-16 8:04 ` Christoph Hellwig
2024-10-16 8:31 ` Ming Lei
2024-10-16 12:31 ` Christoph Hellwig
2024-10-22 1:21 ` Ming Lei
2024-10-22 7:25 ` Christoph Hellwig
2024-10-22 2:15 ` Jens Axboe
2024-10-22 10:24 ` Catalin Marinas
2024-10-23 0:50 ` Ming Lei
2024-10-23 6:12 ` Christoph Hellwig
2024-10-23 8:14 ` Ming Lei
2024-10-23 12:23 ` Christoph Hellwig [this message]
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