Re: [PATCH net 3/3] ice: fix crash on probe for DPLL enabled E810 LOM

[Simon Horman <horms@kernel.org>]

On Mon, Oct 21, 2024 at 04:26:26PM -0700, Jacob Keller wrote:
> From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> 
> The E810 Lan On Motherboard (LOM) design is vendor specific. Intel
> provides the reference design, but it is up to vendor on the final
> product design. For some cases, like Linux DPLL support, the static
> values defined in the driver does not reflect the actual LOM design.
> Current implementation of dpll pins is causing the crash on probe
> of the ice driver for such DPLL enabled E810 LOM designs:
> 
> WARNING: (...) at drivers/dpll/dpll_core.c:495 dpll_pin_get+0x2c4/0x330
> ...
> Call Trace:
>  <TASK>
>  ? __warn+0x83/0x130
>  ? dpll_pin_get+0x2c4/0x330
>  ? report_bug+0x1b7/0x1d0
>  ? handle_bug+0x42/0x70
>  ? exc_invalid_op+0x18/0x70
>  ? asm_exc_invalid_op+0x1a/0x20
>  ? dpll_pin_get+0x117/0x330
>  ? dpll_pin_get+0x2c4/0x330
>  ? dpll_pin_get+0x117/0x330
>  ice_dpll_get_pins.isra.0+0x52/0xe0 [ice]
> ...
> 
> The number of dpll pins enabled by LOM vendor is greater than expected
> and defined in the driver for Intel designed NICs, which causes the crash.
> 
> Prevent the crash and allow generic pin initialization within Linux DPLL
> subsystem for DPLL enabled E810 LOM designs.
> 
> Newly designed solution for described issue will be based on "per HW
> design" pin initialization. It requires pin information dynamically
> acquired from the firmware and is already in progress, planned for
> next-tree only.
> 
> Fixes: d7999f5ea64b ("ice: implement dpll interface to control cgu")
> Reviewed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>

Reviewed-by: Simon Horman <horms@kernel.org>