Re: [RFC PATCH 1/2] hw/arm/sbsa-ref: Enable CXL Host Bridge by pxb-cxl

["Yuquan Wang" <wangyuquan1236@phytium.com.cn>]

Hi，Marcin

I am updating this patches into v2 with Separate MMIO address space for CXL,
however, I'm not confident about the addresss design on sbsa-ref. Below are some
questions about that.

1) With the pxb-cxl-host, any cxl root ports and cxl endpoint devices would occupy the
BDF number of the original pcie domain. Hence, the max available pcie devices on sbsa-ref
would decrease, which seems to bring a series of  trouble.  Do you have any suggestions?

2) In the situation described above, is it necessary to add a separate ecam space for cxl host?



--------------

Many thanks


Yuquan Wang



>On 30.08.2024 06:15, Yuquan Wang wrote:



>> The memory layout places 1M space for 16 host bridge register regions



>> in the sbsa-ref memmap. In addition, this creates a default pxb-cxl



>> (bus_nr=0xfe) bridge with one cxl-rp on sbsa-ref.



>



>With this patchset applied I no longer can add pcie devices to sbsa-ref.



>



>-device nvme,serial=deadbeef,bus=root_port_for_nvme1,drive=hdd



>-drive file=disks/full-debian.hddimg,format=raw,id=hdd,if=none



>



>Normally this adds NVME as pcie device but now it probably ends on 



>pxb-cxl bus instead.



>



>Also please bump platform_version.minor and document adding CXL in 



>docs/system/arm/sbsa.rst file.