From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: <shiju.jose@huawei.com>
Cc: <dave.jiang@intel.com>, <dan.j.williams@intel.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dave@stgolabs.net>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linuxarm@huawei.com>, <tanxiaofei@huawei.com>,
<prime.zeng@hisilicon.com>
Subject: Re: [PATCH v3 2/6] cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
Date: Fri, 25 Oct 2024 13:49:22 +0100 [thread overview]
Message-ID: <20241025134922.0000145f@Huawei.com> (raw)
In-Reply-To: <20241025114555.1363-3-shiju.jose@huawei.com>
On Fri, 25 Oct 2024 12:45:51 +0100
<shiju.jose@huawei.com> wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> Add Component Identifier formatting for CXL spec rev 3.1, Section
> 8.2.9.2.1, Table 8-44.
>
> Examples for Component Identifier format in trace log,
>
> validity_flags='CHANNEL|RANK|DEVICE|COMPONENT|COMPONENT PLDM FORMAT' \
> comp_id=03 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
> comp_id_pldm_valid_flags='PLDM Entity ID | Resource ID' \
> pldm_entity_id=74 c5 08 9a 1a 0b pldm_resource_id=fc d2 7e 2f \
>
> validity_flags='COMPONENT|COMPONENT PLDM FORMAT' \
> comp_id=02 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
> comp_id_pldm_valid_flags='Resource ID' \
> pldm_entity_id=0x00 pldm_resource_id=fc d2 7e 2f
>
> If the validity flags for component ID/component ID format or PLDM ID or
> resource ID are not set, then pldm_entity_id=0x00 or pldm_resource_id=0x00
> would be printed.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Given I can't find any more information in the PLDM specs on how
these might be formatted, this looks like the best we can do.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/trace.h | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
> index 7305974e2301..b508873ce426 100644
> --- a/drivers/cxl/core/trace.h
> +++ b/drivers/cxl/core/trace.h
> @@ -268,6 +268,28 @@ TRACE_EVENT(cxl_generic_event,
> { CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \
> )
>
> +/*
> + * Component ID Format
> + * CXL 3.1 section 8.2.9.2.1; Table 8-44
> + */
> +#define CXL_PLDM_COMPONENT_ID_ENTITY_VALID BIT(0)
> +#define CXL_PLDM_COMPONENT_ID_RES_VALID BIT(1)
> +
> +#define show_comp_id_pldm_flags(flags) __print_flags(flags, " | ", \
> + { CXL_PLDM_COMPONENT_ID_ENTITY_VALID, "PLDM Entity ID" }, \
> + { CXL_PLDM_COMPONENT_ID_RES_VALID, "Resource ID" } \
> +)
> +
> +#define show_pldm_entity_id(flags, valid_comp_id, valid_id_format, comp_id) \
> + (flags & valid_comp_id && flags & valid_id_format) ? \
> + (comp_id[0] & CXL_PLDM_COMPONENT_ID_ENTITY_VALID) ? \
> + __print_hex(&comp_id[1], 6) : "0x00" : "0x00"
> +
> +#define show_pldm_resource_id(flags, valid_comp_id, valid_id_format, comp_id) \
> + (flags & valid_comp_id && flags & valid_id_format) ? \
> + (comp_id[0] & CXL_PLDM_COMPONENT_ID_RES_VALID) ? \
> + __print_hex(&comp_id[7], 4) : "0x00" : "0x00"
> +
> /*
> * General Media Event Record - GMER
> * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
next prev parent reply other threads:[~2024-10-25 12:49 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-25 11:45 [PATCH v3 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
2024-10-25 11:45 ` [PATCH v3 1/6] cxl/events: Update Common Event Record " shiju.jose
2024-10-25 11:45 ` [PATCH v3 2/6] cxl/events: Add Component Identifier formatting for " shiju.jose
2024-10-25 12:49 ` Jonathan Cameron [this message]
2024-10-25 11:45 ` [PATCH v3 3/6] cxl/events: Update General Media Event Record to " shiju.jose
2024-10-25 11:45 ` [PATCH v3 4/6] cxl/events: Update DRAM " shiju.jose
2024-10-25 11:45 ` [PATCH v3 5/6] cxl/events: Update Memory Module " shiju.jose
2024-10-25 11:45 ` [PATCH v3 6/6] cxl/test: Update test code for event records " shiju.jose
2024-10-25 12:50 ` Jonathan Cameron
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