From: "Aneesh Kumar K.V (Arm)" <aneesh.kumar@kernel.org>
To: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>,
Steven Price <steven.price@arm.com>,
Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Joey Gouly <joey.gouly@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
"Aneesh Kumar K.V (Arm)" <aneesh.kumar@kernel.org>
Subject: [PATCH 1/4] arm64: Update the values to binary from hex
Date: Mon, 28 Oct 2024 15:10:11 +0530 [thread overview]
Message-ID: <20241028094014.2596619-2-aneesh.kumar@kernel.org> (raw)
In-Reply-To: <20241028094014.2596619-1-aneesh.kumar@kernel.org>
This matches the ARM ARM representation. No functional change in this
patch.
Signed-off-by: Aneesh Kumar K.V (Arm) <aneesh.kumar@kernel.org>
---
arch/arm64/include/asm/memory.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 0480c61dbb4f..ca42f6d87c16 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -178,17 +178,17 @@
/*
* Memory types for Stage-2 translation
*/
-#define MT_S2_NORMAL 0xf
-#define MT_S2_NORMAL_NC 0x5
-#define MT_S2_DEVICE_nGnRE 0x1
+#define MT_S2_NORMAL 0b1111
+#define MT_S2_NORMAL_NC 0b0101
+#define MT_S2_DEVICE_nGnRE 0b0001
/*
* Memory types for Stage-2 translation when ID_AA64MMFR2_EL1.FWB is 0001
* Stage-2 enforces Normal-WB and Device-nGnRE
*/
-#define MT_S2_FWB_NORMAL 6
-#define MT_S2_FWB_NORMAL_NC 5
-#define MT_S2_FWB_DEVICE_nGnRE 1
+#define MT_S2_FWB_NORMAL 0b0110
+#define MT_S2_FWB_NORMAL_NC 0b0101
+#define MT_S2_FWB_DEVICE_nGnRE 0b0001
#ifdef CONFIG_ARM64_4K_PAGES
#define IOREMAP_MAX_ORDER (PUD_SHIFT)
--
2.43.0
next prev parent reply other threads:[~2024-10-28 9:40 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-28 9:40 [PATCH 0/4] Add support for NoTagAccess memory attribute Aneesh Kumar K.V (Arm)
2024-10-28 9:40 ` Aneesh Kumar K.V (Arm) [this message]
2024-10-28 9:40 ` [PATCH 2/4] arm64: cpufeature: add Allocation Tag Access Permission (MTE_PERM) feature Aneesh Kumar K.V (Arm)
2024-10-28 9:40 ` [PATCH 3/4] arm64: mte: update code comments Aneesh Kumar K.V (Arm)
2024-10-28 10:33 ` Marc Zyngier
2024-10-28 12:47 ` Aneesh Kumar K.V
2024-10-28 18:09 ` Marc Zyngier
2024-10-28 9:40 ` [PATCH 4/4] arm64: mte: Use stage-2 NoTagAccess memory attribute if supported Aneesh Kumar K.V (Arm)
2024-10-28 10:54 ` Marc Zyngier
2024-10-28 13:28 ` Aneesh Kumar K.V
2024-10-28 18:37 ` Marc Zyngier
2024-11-08 7:59 ` Aneesh Kumar K.V
2024-11-12 11:51 ` Marc Zyngier
2024-11-15 16:23 ` Catalin Marinas
2024-10-28 14:44 ` Oliver Upton
2024-10-28 14:52 ` Aneesh Kumar K.V
2024-10-28 15:07 ` Oliver Upton
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