All of lore.kernel.org
 help / color / mirror / Atom feed
From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
	qemu-ppc@nongnu.org, "Harsh Prateek Bora" <harshpb@linux.ibm.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Cédric Le Goater" <clg@redhat.com>
Subject: [PULL 29/67] ppc/spapr: remove deprecated machine pseries-2.12
Date: Mon,  4 Nov 2024 10:18:18 +1000	[thread overview]
Message-ID: <20241104001900.682660-30-npiggin@gmail.com> (raw)
In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com>

From: Harsh Prateek Bora <harshpb@linux.ibm.com>

Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated
with reasons mentioned in its commit log.
Removing pseries-2.12 specific code with this patch.

While at it, also remove pre-3.0-migration hacks introduced for backward
compatibility which are now turned useless.

Suggested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 docs/about/deprecated.rst       |  8 --------
 hw/ppc/spapr.c                  | 25 -------------------------
 hw/ppc/spapr_cpu_core.c         | 12 +++---------
 include/hw/ppc/spapr_cpu_core.h |  1 -
 target/ppc/cpu.h                |  4 ----
 target/ppc/cpu_init.c           |  3 +--
 target/ppc/machine.c            | 18 +-----------------
 7 files changed, 5 insertions(+), 66 deletions(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 1e1e9f5f18..756186f4f0 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -243,14 +243,6 @@ These old machine types are quite neglected nowadays and thus might have
 various pitfalls with regards to live migration. Use a newer machine type
 instead.
 
-``pseries-2.1`` up to ``pseries-2.12`` (since 9.0)
-''''''''''''''''''''''''''''''''''''''''''''''''''
-
-Older pseries machines before version 3.0 have undergone many changes
-to correct issues, mostly regarding migration compatibility. These are
-no longer maintained and removing them will make the code easier to
-read and maintain. Use versions 3.0 and above as a replacement.
-
 PPC 405 ``ref405ep`` machine (since 9.1)
 ''''''''''''''''''''''''''''''''''''''''
 
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index aba0ad26f1..5c02037c56 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -5015,31 +5015,6 @@ static void spapr_machine_3_0_class_options(MachineClass *mc)
 
 DEFINE_SPAPR_MACHINE(3, 0);
 
-/*
- * pseries-2.12
- */
-static void spapr_machine_2_12_class_options(MachineClass *mc)
-{
-    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
-    static GlobalProperty compat[] = {
-        { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" },
-        { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" },
-    };
-
-    spapr_machine_3_0_class_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
-    compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
-
-    /* We depend on kvm_enabled() to choose a default value for the
-     * hpt-max-page-size capability. Of course we can't do it here
-     * because this is too early and the HW accelerator isn't initialized
-     * yet. Postpone this to machine init (see default_caps_with_cpu()).
-     */
-    smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
-}
-
-DEFINE_SPAPR_MACHINE(2, 12);
-
 static void spapr_machine_register_types(void)
 {
     type_register_static(&spapr_machine_info);
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 4642245168..1a84345f36 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -197,9 +197,7 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 {
     CPUPPCState *env = &cpu->env;
 
-    if (!sc->pre_3_0_migration) {
-        vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
-    }
+    vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
     spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu);
     cpu_ppc_tb_free(env);
     qdev_unrealize(DEVICE(cpu));
@@ -285,10 +283,8 @@ static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
         return false;
     }
 
-    if (!sc->pre_3_0_migration) {
-        vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
-                         cpu->machine_data);
-    }
+    vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
+                     cpu->machine_data);
     return true;
 }
 
@@ -366,8 +362,6 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 
 static Property spapr_cpu_core_properties[] = {
     DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
-    DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
-                     false),
     DEFINE_PROP_END_OF_LIST()
 };
 
diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h
index 69a52e39b8..68f7083483 100644
--- a/include/hw/ppc/spapr_cpu_core.h
+++ b/include/hw/ppc/spapr_cpu_core.h
@@ -28,7 +28,6 @@ struct SpaprCpuCore {
     /*< public >*/
     PowerPCCPU **threads;
     int node_id;
-    bool pre_3_0_migration; /* older machine don't know about SpaprCpuState */
 };
 
 struct SpaprCpuCoreClass {
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index faa610197d..b838bc2ab9 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1455,10 +1455,6 @@ struct ArchCPU {
     /* Those resources are used only during code translation */
     /* opcode handlers */
     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
-
-    /* Fields related to migration compatibility hacks */
-    bool pre_3_0_migration;
-    int32_t mig_slb_nr;
 };
 
 /**
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 39c19e6674..011e53d961 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7452,8 +7452,7 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
 }
 
 static Property ppc_cpu_properties[] = {
-    DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
-                     false),
+    /* add default property here */
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 47495b68b1..717bf93e88 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -118,15 +118,6 @@ static const VMStateInfo vmstate_info_vsr = {
 #define VMSTATE_VSR_ARRAY(_f, _s, _n)                             \
     VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0)
 
-#if defined(TARGET_PPC64)
-static bool cpu_pre_3_0_migration(void *opaque, int version_id)
-{
-    PowerPCCPU *cpu = opaque;
-
-    return cpu->pre_3_0_migration;
-}
-#endif
-
 static int cpu_pre_save(void *opaque)
 {
     PowerPCCPU *cpu = opaque;
@@ -154,12 +145,6 @@ static int cpu_pre_save(void *opaque)
         env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4];
     }
 
-    if (cpu->pre_3_0_migration) {
-        if (cpu->hash64_opts) {
-            cpu->mig_slb_nr = cpu->hash64_opts->slb_size;
-        }
-    }
-
     /* Used to retain migration compatibility for pre 6.0 for 601 machines. */
     env->hflags_compat_nmsr = 0;
 
@@ -503,12 +488,11 @@ static int slb_post_load(void *opaque, int version_id)
 
 static const VMStateDescription vmstate_slb = {
     .name = "cpu/slb",
-    .version_id = 1,
+    .version_id = 2,
     .minimum_version_id = 1,
     .needed = slb_needed,
     .post_load = slb_post_load,
     .fields = (const VMStateField[]) {
-        VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration),
         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
         VMSTATE_END_OF_LIST()
     }
-- 
2.45.2



  parent reply	other threads:[~2024-11-04  0:22 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-04  0:17 [PULL 00/67] ppc-for-9.2-1 queue Nicholas Piggin
2024-11-04  0:17 ` [PULL 01/67] target/ppc: Set ctx->opcode for decode_insn32() Nicholas Piggin
2024-11-04  0:17 ` [PULL 02/67] target/ppc: Make divd[u] handler method decodetree compatible Nicholas Piggin
2024-11-05 15:33   ` Michael Tokarev
2024-11-05 18:01     ` Ilya Leoshkevich
2024-11-05 18:45       ` Michael Tokarev
2024-11-04  0:17 ` [PULL 03/67] ppc/pnv: Fix LPC serirq routing calculation Nicholas Piggin
2024-11-04  0:17 ` [PULL 04/67] ppc/pnv: Fix LPC POWER8 register sanity check Nicholas Piggin
2024-11-04  0:17 ` [PULL 05/67] target/ppc: Fix mtDPDES targeting SMT siblings Nicholas Piggin
2024-11-04  0:17 ` [PULL 06/67] target/ppc: PMIs are level triggered Nicholas Piggin
2024-11-04  0:17 ` [PULL 07/67] target/ppc: Fix doorbell delivery to threads in powersave Nicholas Piggin
2024-11-04  0:17 ` [PULL 08/67] target/ppc: Fix HFSCR facility checks Nicholas Piggin
2024-11-05 15:50   ` Michael Tokarev
2024-11-08  2:34     ` Nicholas Piggin
2024-11-04  0:17 ` [PULL 09/67] target/ppc: Fix VRMA to not check virtual page class key protection Nicholas Piggin
2024-11-04  0:17 ` [PULL 10/67] ppc/pnv: ADU fix possible buffer overrun with invalid size Nicholas Piggin
2024-11-04  0:18 ` [PULL 11/67] MAINTAINERS: Cover PowerPC SPI model in PowerNV section Nicholas Piggin
2024-11-04  0:18 ` [PULL 12/67] hw/ssi/pnv_spi: Match _xfer_buffer_free() with _xfer_buffer_new() Nicholas Piggin
2024-11-04  0:18 ` [PULL 13/67] hw/ssi/pnv_spi: Return early in transfer() Nicholas Piggin
2024-11-04  0:18 ` [PULL 14/67] hw/ssi/pnv_spi: Fixes Coverity CID 1558831 Nicholas Piggin
2024-11-04  0:18 ` [PULL 15/67] tests/tcg: Replace -mpower8-vector with -mcpu=power8 Nicholas Piggin
2024-11-04  0:18 ` [PULL 16/67] hw/ppc: fix decrementer with BookE timers Nicholas Piggin
2024-11-04  0:18 ` [PULL 17/67] ppc/spapr: remove deprecated machine pseries-2.1 Nicholas Piggin
2024-11-04  0:18 ` [PULL 18/67] ppc/spapr: remove deprecated machine pseries-2.2 Nicholas Piggin
2024-11-04  0:18 ` [PULL 19/67] ppc/spapr: remove deprecated machine pseries-2.3 Nicholas Piggin
2024-11-04  0:18 ` [PULL 20/67] ppc/spapr: remove deprecated machine pseries-2.4 Nicholas Piggin
2024-11-04  0:18 ` [PULL 21/67] ppc/spapr: remove deprecated machine pseries-2.5 Nicholas Piggin
2024-11-04  0:18 ` [PULL 22/67] ppc/spapr: remove deprecated machine pseries-2.6 Nicholas Piggin
2024-11-04  0:18 ` [PULL 23/67] ppc/spapr: remove deprecated machine pseries-2.7 Nicholas Piggin
2024-11-04  0:18 ` [PULL 24/67] ppc/spapr: remove deprecated machine pseries-2.8 Nicholas Piggin
2024-11-04  0:18 ` [PULL 25/67] ppc/spapr: remove deprecated machine pseries-2.9 Nicholas Piggin
2024-11-04  0:18 ` [PULL 26/67] ppc/spapr: remove deprecated machine pseries-2.10 Nicholas Piggin
2024-11-04  0:18 ` [PULL 27/67] ppc/spapr: remove deprecated machine pseries-2.11 Nicholas Piggin
2024-11-04  0:18 ` [PULL 28/67] ppc/spapr: remove deprecated machine pseries-2.12-sxxm Nicholas Piggin
2024-11-04  0:18 ` Nicholas Piggin [this message]
2024-11-04  0:18 ` [PULL 30/67] target/ppc: Reduce code duplication across Power9/10 init code Nicholas Piggin
2024-11-04  0:18 ` [PULL 31/67] target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr' Nicholas Piggin
2024-11-04  0:18 ` [PULL 32/67] target/ppc: Fix regression due to Power10 and Power11 having same PCR Nicholas Piggin
2024-11-04  0:18 ` [PULL 33/67] target/ppc: Add Power11 DD2.0 processor Nicholas Piggin
2024-11-04  0:18 ` [PULL 34/67] ppc/pseries: Add Power11 cpu type Nicholas Piggin
2024-11-04  0:18 ` [PULL 35/67] target/ppc: use locally stored msr and avoid indirect access Nicholas Piggin
2024-11-04  0:18 ` [PULL 36/67] target/ppc: optimize hreg_compute_pmu_hflags_value Nicholas Piggin
2024-11-04  0:18 ` [PULL 37/67] " Nicholas Piggin
2024-11-04  0:18 ` [PULL 38/67] target/ppc: optimize p9 exception handling routines Nicholas Piggin
2024-11-04  0:18 ` [PULL 39/67] target/ppc: optimize p8 " Nicholas Piggin
2024-11-04  0:18 ` [PULL 40/67] target/ppc: optimize p7 " Nicholas Piggin
2024-11-04  0:18 ` [PULL 41/67] target/ppc: simplify var usage in ppc_next_unmasked_interrupt Nicholas Piggin
2024-11-04  0:18 ` [PULL 42/67] target/ppc: combine multiple ail checks into one Nicholas Piggin
2024-11-04  0:18 ` [PULL 43/67] target/ppc: reduce duplicate code between init_proc_POWER{9, 10} Nicholas Piggin
2024-11-04  0:18 ` [PULL 44/67] spapr: nested: Add support for DPDES SPR in GSB for TCG L0 Nicholas Piggin
2024-11-04  0:18 ` [PULL 45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in " Nicholas Piggin
2024-11-04  0:18 ` [PULL 46/67] hw/ppc: Implement -dtb support for PowerNV Nicholas Piggin
2024-11-04  0:18 ` [PULL 47/67] ppc/xive: Fix ESB length overflow on 32-bit hosts Nicholas Piggin
2024-11-04  0:18 ` [PULL 48/67] pnv/xive: TIMA patch sets pre-req alignment and formatting changes Nicholas Piggin
2024-11-04  0:18 ` [PULL 49/67] pnv/xive2: Define OGEN field in the TIMA Nicholas Piggin
2024-11-04  0:18 ` [PULL 50/67] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" Nicholas Piggin
2024-11-04  0:18 ` [PULL 51/67] pnv/xive2: Support for "OS LGS Push" TIMA operation Nicholas Piggin
2024-11-04  0:18 ` [PULL 52/67] ppc/xive2: Dump more NVP state with 'info pic' Nicholas Piggin
2024-11-04  0:18 ` [PULL 53/67] ppc/xive2: Dump the VP-group and crowd tables " Nicholas Piggin
2024-11-04  0:18 ` [PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA Nicholas Piggin
2024-11-04  0:18 ` [PULL 55/67] ppc/xive2: Support "Pull Thread Context to Register" operation Nicholas Piggin
2024-11-04  0:18 ` [PULL 56/67] ppc/xive2: Change context/ring specific functions to be generic Nicholas Piggin
2024-11-04  0:18 ` [PULL 57/67] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" Nicholas Piggin
2024-11-04  0:18 ` [PULL 58/67] pnv/xive: Add special handling for pool targets Nicholas Piggin
2024-11-04  0:18 ` [PULL 59/67] pnv/xive: Update PIPR when updating CPPR Nicholas Piggin
2024-11-04  0:18 ` [PULL 60/67] pnv/xive2: TIMA support for 8-byte OS context push for PHYP Nicholas Piggin
2024-11-04  0:18 ` [PULL 61/67] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths Nicholas Piggin
2024-11-04  0:18 ` [PULL 62/67] tests/qtest: Add XIVE tests for the powernv10 machine Nicholas Piggin
2024-11-04  0:18 ` [PULL 63/67] hw/ppc: Consolidate e500 initial mapping creation functions Nicholas Piggin
2024-11-04  0:18 ` [PULL 64/67] hw/ppc: Consolidate ppc440 " Nicholas Piggin
2024-11-04  0:18 ` [PULL 65/67] MAINTAINERS: Remove myself from the PowerNV machines Nicholas Piggin
2024-11-04  0:18 ` [PULL 66/67] MAINTAINERS: Remove myself from XIVE Nicholas Piggin
2024-11-04  0:18 ` [PULL 67/67] MAINTAINERS: Remove myself as reviewer Nicholas Piggin
2024-11-05 14:22 ` [PULL 00/67] ppc-for-9.2-1 queue Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20241104001900.682660-30-npiggin@gmail.com \
    --to=npiggin@gmail.com \
    --cc=clg@kaod.org \
    --cc=clg@redhat.com \
    --cc=harshpb@linux.ibm.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.