From: Jason Gunthorpe <jgg@nvidia.com>
To: Uros Bizjak <ubizjak@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
Joerg Roedel <joro@8bytes.org>,
Robin Murphy <robin.murphy@arm.com>,
vasant.hegde@amd.com, Linux-Arch <linux-arch@vger.kernel.org>,
Kevin Tian <kevin.tian@intel.com>,
jon.grimm@amd.com, santosh.shukla@amd.com, pandoh@google.com,
kumaranand@google.com
Subject: Re: [PATCH v10 05/10] iommu/amd: Introduce helper function to update 256-bit DTE
Date: Wed, 13 Nov 2024 10:28:07 -0400 [thread overview]
Message-ID: <20241113142807.GJ35230@nvidia.com> (raw)
In-Reply-To: <CAFULd4aGDM5ySO-PeOH0+_U89mnqYqQ7v+U0ZsMode3bxs_X7w@mail.gmail.com>
On Wed, Nov 13, 2024 at 03:14:09PM +0100, Uros Bizjak wrote:
> > > Even without atomicity guarantee, __READ_ONCE() still prevents the
> > > compiler from performing unwanted optimizations (please see the first
> > > comment in include/asm-generic/rwonce.h) and unwanted reordering of
> > > reads and writes when this function is inlined. This macro does cast
> > > the read to volatile, but IMO it is much more readable to use
> > > __READ_ONCE() than volatile qualifier.
> >
> > Yes it does, but please explain to me what "unwanted reordering" is
> > allowed here?
>
> It is a static function that will be inlined by the compiler
> somewhere, so "unwanted reordering" depends on where it will be
> inlined. *IF* it will be called from safe code, then this limitation
> for the compiler can be lifted.
As long as the values are read within the spinlock the order does not
matter. READ_ONCE() is not required to contain reads within spinlocks.
Jason
next prev parent reply other threads:[~2024-11-13 14:28 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-13 12:03 [PATCH v10 00/10] iommu/amd: Use 128-bit cmpxchg operation to update DTE Suravee Suthikulpanit
2024-11-13 12:03 ` [PATCH v10 01/10] iommu/amd: Misc ACPI IVRS debug info clean up Suravee Suthikulpanit
2024-11-13 12:03 ` [PATCH v10 02/10] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported Suravee Suthikulpanit
2024-11-13 12:35 ` Arnd Bergmann
2024-11-13 12:03 ` [PATCH v10 03/10] compiler_types.h: Introduce 128-bit unqualified scalar type support Suravee Suthikulpanit
2024-11-13 12:03 ` [PATCH v10 04/10] iommu/amd: Introduce struct ivhd_dte_flags to store persistent DTE flags Suravee Suthikulpanit
2024-11-13 12:03 ` [PATCH v10 05/10] iommu/amd: Introduce helper function to update 256-bit DTE Suravee Suthikulpanit
2024-11-13 12:50 ` Arnd Bergmann
2024-11-13 13:20 ` Jason Gunthorpe
2024-11-13 14:06 ` Uros Bizjak
2024-11-13 14:09 ` Jason Gunthorpe
2024-11-13 14:14 ` Uros Bizjak
2024-11-13 14:28 ` Jason Gunthorpe [this message]
2024-11-13 14:36 ` Uros Bizjak
2024-11-13 16:34 ` Jason Gunthorpe
2024-11-13 19:50 ` Uros Bizjak
2024-11-13 20:08 ` Uros Bizjak
2024-11-14 16:29 ` Jason Gunthorpe
2024-11-14 20:25 ` Uros Bizjak
2024-11-13 12:03 ` [PATCH v10 06/10] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers Suravee Suthikulpanit
2024-11-13 12:03 ` [PATCH v10 07/10] iommu/amd: Introduce helper function get_dte256() Suravee Suthikulpanit
2024-11-13 12:03 ` [PATCH v10 08/10] iommu/amd: Modify clear_dte_entry() to avoid in-place update Suravee Suthikulpanit
2024-11-13 12:03 ` [PATCH v10 09/10] iommu/amd: Lock DTE before updating the entry with WRITE_ONCE() Suravee Suthikulpanit
2024-11-13 12:03 ` [PATCH v10 10/10] iommu/amd: Remove amd_iommu_apply_erratum_63() Suravee Suthikulpanit
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