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From: Sasha Levin <sashal@kernel.org>
To: stable@vger.kernel.org
Cc: Bin Lan <bin.lan.cn@windriver.com>, Sasha Levin <sashal@kernel.org>
Subject: Re: [PATCH 6.6] serial: sc16is7xx: fix invalid FIFO access with special register set
Date: Fri, 22 Nov 2024 08:51:47 -0500	[thread overview]
Message-ID: <20241122083228-3df619e519e722b2@stable.kernel.org> (raw)
In-Reply-To: <20241122064331.3863447-1-bin.lan.cn@windriver.com>

[ Sasha's backport helper bot ]

Hi,

The upstream commit SHA1 provided is correct: 7d3b793faaab1305994ce568b59d61927235f57b

WARNING: Author mismatch between patch and upstream commit:
Backport author: Bin Lan <bin.lan.cn@windriver.com>
Commit author: Hugo Villeneuve <hvilleneuve@dimonoff.com>


Status in newer kernel trees:
6.12.y | Present (exact SHA1)
6.11.y | Present (exact SHA1)
6.6.y | Not found

Note: The patch differs from the upstream commit:
---
--- -	2024-11-22 08:26:44.256901766 -0500
+++ /tmp/tmp.CWNfMe5MUW	2024-11-22 08:26:44.252793305 -0500
@@ -1,3 +1,5 @@
+[ Upstream commit 7d3b793faaab1305994ce568b59d61927235f57b ]
+
 When enabling access to the special register set, Receiver time-out and
 RHR interrupts can happen. In this case, the IRQ handler will try to read
 from the FIFO thru the RHR register at address 0x00, but address 0x00 is
@@ -22,25 +24,27 @@
 Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
 Link: https://lore.kernel.org/r/20240723125302.1305372-3-hugo@hugovil.com
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+[ Resolve minor conflicts ]
+Signed-off-by: Bin Lan <bin.lan.cn@windriver.com>
 ---
  drivers/tty/serial/sc16is7xx.c | 4 ++++
  1 file changed, 4 insertions(+)
 
 diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
-index 58696e05492ca..b4c1798a1df2a 100644
+index 7a9924d9b294..f290fbe21d63 100644
 --- a/drivers/tty/serial/sc16is7xx.c
 +++ b/drivers/tty/serial/sc16is7xx.c
-@@ -592,6 +592,8 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud)
+@@ -545,6 +545,8 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud)
  			      SC16IS7XX_MCR_CLKSEL_BIT,
  			      prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);
  
 +	mutex_lock(&one->efr_lock);
 +
- 	/* Backup LCR and access special register set (DLL/DLH) */
- 	lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
+ 	/* Open the LCR divisors for configuration */
  	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
-@@ -606,6 +608,8 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud)
- 	/* Restore LCR and access to general register set */
+ 			     SC16IS7XX_LCR_CONF_MODE_A);
+@@ -558,6 +560,8 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud)
+ 	/* Put LCR back to the normal mode */
  	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
  
 +	mutex_unlock(&one->efr_lock);
@@ -48,3 +52,6 @@
  	return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);
  }
  
+-- 
+2.43.0
+
---

Results of testing on various branches:

| Branch                    | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-6.6.y        |  Success    |  Success   |

  reply	other threads:[~2024-11-22 13:51 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-22  6:43 [PATCH 6.6] serial: sc16is7xx: fix invalid FIFO access with special register set Bin Lan
2024-11-22 13:51 ` Sasha Levin [this message]
  -- strict thread matches above, loose matches on Subject: below --
2024-11-26  2:18 Bin Lan
2024-11-26  3:13 ` Sasha Levin
2024-11-26  6:07   ` Bin Lan

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