diff for duplicates of <20241125-23cfeccc06900429ecd2a31d@orel> diff --git a/a/1.txt b/N1/1.txt index cb8ccae..098cd76 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,13 +1,13 @@ -On Mon, Nov 25, 2024 at 03:13:01PM +0100, Cl?ment L?ger wrote: +On Mon, Nov 25, 2024 at 03:13:01PM +0100, Clément Léger wrote: > > > On 25/11/2024 14:50, Andrew Jones wrote: -> > On Mon, Nov 25, 2024 at 12:54:47PM +0100, Cl?ment L?ger wrote: +> > On Mon, Nov 25, 2024 at 12:54:47PM +0100, Clément Léger wrote: > >> Add a SSE entry assembly code to handle SSE events. Events should be > >> registered with a struct sse_handler_arg containing a correct stack and > >> handler function. > >> -> >> Signed-off-by: Cl?ment L?ger <cleger@rivosinc.com> +> >> Signed-off-by: Clément Léger <cleger@rivosinc.com> > >> --- > >> riscv/Makefile | 1 + > >> lib/riscv/asm/sse.h | 16 +++++++ @@ -70,7 +70,7 @@ On Mon, Nov 25, 2024 at 03:13:01PM +0100, Cl?ment L?ger wrote: > >> +/* > >> + * SBI SSE entry code > >> + * -> >> + * Copyright (C) 2024, Rivos Inc., Cl?ment L?ger <cleger@rivosinc.com> +> >> + * Copyright (C) 2024, Rivos Inc., Clément Léger <cleger@rivosinc.com> > >> + */ > >> +#include <asm/asm.h> > >> +#include <asm/asm-offsets.h> @@ -265,7 +265,7 @@ On Mon, Nov 25, 2024 at 03:13:01PM +0100, Cl?ment L?ger wrote: > > -/* > > - * SBI SSE entry code > > - * -> > - * Copyright (C) 2024, Rivos Inc., Cl?ment L?ger <cleger@rivosinc.com> +> > - * Copyright (C) 2024, Rivos Inc., Clément Léger <cleger@rivosinc.com> > > - */ > > -#include <asm/asm.h> > > -#include <asm/asm-offsets.h> diff --git a/a/content_digest b/N1/content_digest index af18f61..e103942 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,21 +3,26 @@ "ref\020241125-46efbc121d5164de961a804e@orel\0" "ref\05853b922-da5a-409e-875b-084da78999bd@rivosinc.com\0" "From\0Andrew Jones <andrew.jones@linux.dev>\0" - "Subject\0[kvm-unit-tests PATCH v3 3/4] riscv: lib: Add SSE assembly entry handling\0" + "Subject\0Re: [kvm-unit-tests PATCH v3 3/4] riscv: lib: Add SSE assembly entry handling\0" "Date\0Mon, 25 Nov 2024 15:26:49 +0100\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0Cl\303\251ment L\303\251ger <cleger@rivosinc.com>\0" + "Cc\0kvm@vger.kernel.org" + kvm-riscv@lists.infradead.org + Andrew Jones <ajones@ventanamicro.com> + Anup Patel <apatel@ventanamicro.com> + " Atish Patra <atishp@rivosinc.com>\0" "\00:1\0" "b\0" - "On Mon, Nov 25, 2024 at 03:13:01PM +0100, Cl?ment L?ger wrote:\n" + "On Mon, Nov 25, 2024 at 03:13:01PM +0100, Cl\303\251ment L\303\251ger wrote:\n" "> \n" "> \n" "> On 25/11/2024 14:50, Andrew Jones wrote:\n" - "> > On Mon, Nov 25, 2024 at 12:54:47PM +0100, Cl?ment L?ger wrote:\n" + "> > On Mon, Nov 25, 2024 at 12:54:47PM +0100, Cl\303\251ment L\303\251ger wrote:\n" "> >> Add a SSE entry assembly code to handle SSE events. Events should be\n" "> >> registered with a struct sse_handler_arg containing a correct stack and\n" "> >> handler function.\n" "> >>\n" - "> >> Signed-off-by: Cl?ment L?ger <cleger@rivosinc.com>\n" + "> >> Signed-off-by: Cl\303\251ment L\303\251ger <cleger@rivosinc.com>\n" "> >> ---\n" "> >> riscv/Makefile | 1 +\n" "> >> lib/riscv/asm/sse.h | 16 +++++++\n" @@ -80,7 +85,7 @@ "> >> +/*\n" "> >> + * SBI SSE entry code\n" "> >> + *\n" - "> >> + * Copyright (C) 2024, Rivos Inc., Cl?ment L?ger <cleger@rivosinc.com>\n" + "> >> + * Copyright (C) 2024, Rivos Inc., Cl\303\251ment L\303\251ger <cleger@rivosinc.com>\n" "> >> + */\n" "> >> +#include <asm/asm.h>\n" "> >> +#include <asm/asm-offsets.h>\n" @@ -275,7 +280,7 @@ "> > -/*\n" "> > - * SBI SSE entry code\n" "> > - *\n" - "> > - * Copyright (C) 2024, Rivos Inc., Cl?ment L?ger <cleger@rivosinc.com>\n" + "> > - * Copyright (C) 2024, Rivos Inc., Cl\303\251ment L\303\251ger <cleger@rivosinc.com>\n" "> > - */\n" "> > -#include <asm/asm.h>\n" "> > -#include <asm/asm-offsets.h>\n" @@ -567,4 +572,4 @@ "Thanks,\n" drew -973d88405433e090d4030b26c7e1c597b7dfbea55017f9e8e2af944752b8f2b8 +12700961a80cc7ae2048ec2e82790666611389c83a458bc0e0b9d5097c752ab2
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