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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 1/8] hw/pci/pci_bus: Introduce PCIBusFlags::PCI_BUS_IO_ADDR0_ALLOWED Date: Mon, 25 Nov 2024 15:05:28 +0100 Message-ID: <20241125140535.4526-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Some machines need PCI buses to allow access at BAR0. Introduce the PCI_BUS_IO_ADDR0_ALLOWED flag and the pci_bus_allows_io_addr0_access() helper, so machines can set this flag during creation, similarly to how they do with the PCI_BUS_EXTENDED_CONFIG_SPACE flag. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci_bus.h | 6 ++++++ hw/pci/pci.c | 1 + 2 files changed, 7 insertions(+) diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 2261312546..5c8b0d2887 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -26,6 +26,7 @@ enum PCIBusFlags { PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002, /* This is a CXL Type BUS */ PCI_BUS_CXL = 0x0004, + PCI_BUS_IO_ADDR0_ALLOWED = 0x0008, }; #define PCI_NO_PASID UINT32_MAX @@ -72,4 +73,9 @@ static inline bool pci_bus_allows_extended_config_space(PCIBus *bus) return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE); } +static inline bool pci_bus_allows_io_addr0_access(PCIBus *bus) +{ + return !!(bus->flags & PCI_BUS_IO_ADDR0_ALLOWED); +} + #endif /* QEMU_PCI_BUS_H */ diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 1416ae202c..de3f93646f 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -1475,6 +1475,7 @@ pcibus_t pci_bar_address(PCIDevice *d, MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); bool allow_0_address = mc->pci_allow_0_address; + allow_0_address |= pci_bus_allows_io_addr0_access(pci_get_bus(d)); if (type & PCI_BASE_ADDRESS_SPACE_IO) { if (!(cmd & PCI_COMMAND_IO)) { return PCI_BAR_UNMAPPED; -- 2.45.2