From: Peter Zijlstra <peterz@infradead.org>
To: Mario Limonciello <mario.limonciello@amd.com>
Cc: Borislav Petkov <bp@alien8.de>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
<x86@kernel.org>, "H . Peter Anvin" <hpa@zytor.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Gautham R . Shenoy" <gautham.shenoy@amd.com>,
Perry Yuan <perry.yuan@amd.com>,
Brijesh Singh <brijesh.singh@amd.com>,
Li RongQing <lirongqing@baidu.com>,
"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
<linux-kernel@vger.kernel.org>,
"open list:ACPI" <linux-acpi@vger.kernel.org>,
"open list:AMD PSTATE DRIVER" <linux-pm@vger.kernel.org>,
Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
Bagas Sanjaya <bagasdotme@gmail.com>
Subject: Re: [PATCH v7 01/12] Documentation: x86: Add AMD Hardware Feedback Interface documentation
Date: Mon, 2 Dec 2024 12:45:13 +0100 [thread overview]
Message-ID: <20241202114513.GD8562@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20241130140703.557-2-mario.limonciello@amd.com>
On Sat, Nov 30, 2024 at 08:06:52AM -0600, Mario Limonciello wrote:
> +Thread Classification and Ranking Table Interaction
> +----------------------------------------------------
> +
> +The thread classification is used to select into a ranking table that describes
> +an efficiency and performance ranking for each classification.
> +
> +Threads are classified during runtime into enumerated classes. The classes represent
> +thread performance/power characteristics that may benefit from special scheduling behaviors.
> +The below table depicts an example of thread classification and a preference where a given thread
> +should be scheduled based on its thread class. The real time thread classification is consumed
> +by the operating system and is used to inform the scheduler of where the thread should be placed.
> +
> +Thread Classification Example Table
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> ++----------+----------------+-------------------------------+---------------------+---------+
> +| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter |
> ++----------+----------------+-------------------------------+---------------------+---------+
> +| 0 | Default | Performant | Highest | |
> ++----------+----------------+-------------------------------+---------------------+---------+
> +| 1 | Non-scalable | Efficient | Lowest | PMCx1A1 |
> ++----------+----------------+-------------------------------+---------------------+---------+
> +| 2 | I/O bound | Efficient | Lowest | PMCx044 |
> ++----------+----------------+-------------------------------+---------------------+---------+
> +
> +Thread classification is performed by the hardware each time that the thread is switched out.
> +Threads that don't meet any hardware specified criteria will be classified as "default".
I'm not seeing this part in the patches, am I needing to read more
careful?
next prev parent reply other threads:[~2024-12-02 11:45 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-30 14:06 [PATCH v7 00/12] Add support for AMD hardware feedback interface Mario Limonciello
2024-11-30 14:06 ` [PATCH v7 01/12] Documentation: x86: Add AMD Hardware Feedback Interface documentation Mario Limonciello
2024-12-02 11:45 ` Peter Zijlstra [this message]
2024-12-03 20:30 ` Mario Limonciello
2024-11-30 14:06 ` [PATCH v7 02/12] MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Mario Limonciello
2024-11-30 14:06 ` [PATCH v7 03/12] x86/msr-index: define AMD heterogeneous CPU related MSR Mario Limonciello
2024-11-30 14:06 ` [PATCH v7 04/12] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver Mario Limonciello
2024-12-02 11:35 ` Peter Zijlstra
2024-12-03 20:27 ` Mario Limonciello
2024-12-05 9:08 ` Peter Zijlstra
2024-11-30 14:06 ` [PATCH v7 05/12] platform/x86: hfi: parse CPU core ranking data from shared memory Mario Limonciello
2024-11-30 14:06 ` [PATCH v7 06/12] platform/x86: hfi: init per-cpu scores for each class Mario Limonciello
2024-11-30 14:06 ` [PATCH v7 07/12] platform/x86: hfi: add online and offline callback support Mario Limonciello
2024-12-02 11:38 ` Peter Zijlstra
2024-12-03 20:28 ` Mario Limonciello
2024-12-05 9:09 ` Peter Zijlstra
2024-11-30 14:06 ` [PATCH v7 08/12] platform/x86: hfi: add power management callback Mario Limonciello
2024-11-30 14:07 ` [PATCH v7 09/12] x86/process: Clear hardware feedback history for AMD processors Mario Limonciello
2024-12-02 11:40 ` Peter Zijlstra
2024-12-02 15:59 ` Peter Zijlstra
2024-12-03 21:56 ` Mario Limonciello
2024-12-02 16:38 ` Dave Hansen
2024-11-30 14:07 ` [PATCH v7 10/12] cpufreq/amd-pstate: Disable preferred cores on designs with workload classification Mario Limonciello
2024-11-30 14:07 ` [PATCH v7 11/12] platform/x86/amd: hfi: Set ITMT priority from ranking data Mario Limonciello
2024-11-30 14:07 ` [PATCH v7 12/12] platform/x86/amd: hfi: Add debugfs support Mario Limonciello
-- strict thread matches above, loose matches on Subject: below --
2024-11-30 15:20 [PATCH v7 00/12] Add support for AMD hardware feedback interface Mario Limonciello
2024-11-30 15:20 ` [PATCH v7 01/12] Documentation: x86: Add AMD Hardware Feedback Interface documentation Mario Limonciello
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